Add beaglebone target files
This commit is contained in:
Corey Vixie
parent
99d5992d5e
commit
f3d12e7cc2
347
platforms/beaglebone/VE-2IN-BBB.dts
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347
platforms/beaglebone/VE-2IN-BBB.dts
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/**
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* Copyright (C) 2019 Corey Vixie
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*/
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/dts-v1/;
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/plugin/;
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/pinctrl/am33xx.h>
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#include <dt-bindings/board/am335x-bbw-bbb-base.h>
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/ {
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compatible = "ti,beaglebone", "ti,beaglebone-black", "ti,beaglebone-green";
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/* ID */
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part-number = "VE-2IN-LCD";
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version = "00A0";
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/* Reserved Pins */
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exclusive-use =
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/* TIED LOW / GND : Blue 5 (LSB) */
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"P8.45", /* LCD_DATA0 : Blue 4 */
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"P8.46", /* LCD_DATA1 : Blue 3 */
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"P8.43", /* LCD_DATA2 : Blue 2 */
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"P8.44", /* LCD_DATA3 : Blue 1 */
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"P8.41", /* LCD_DATA4 : Blue 0 (MSB) */
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"P8.42", /* LCD_DATA5 : Green 5 (LSB) */
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"P8.39", /* LCD_DATA6 : Green 4 */
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"P8.40", /* LCD_DATA7 : Green 3 */
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"P8.37", /* LCD_DATA8 : Green 2 */
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"P8.38", /* LCD_DATA9 : Green 1 */
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"P8.36", /* LCD_DATA10 : Green 0 (MSB) */
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/* TIED LOW / GND : Red 5 (LSB) */
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"P8.34", /* LCD_DATA11 : Red 4 */
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"P8.35", /* LCD_DATA12 : Red 3 */
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"P8.33", /* LCD_DATA13 : Red 2 */
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"P8.31", /* LCD_DATA14 : Red 1 */
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"P8.32", /* LCD_DATA15 : Red 0 (MSB) */
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"P8.15", /* gpmc_ad15.lcd_data16 */
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"P8.16", /* gpmc_ad14.lcd_data17 */
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"P8.11", /* gpmc_ad13.lcd_data18 */
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"P8.12", /* gpmc_ad12.lcd_data19 */
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"P8.17", /* gpmc_ad11.lcd_data20 */
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"P8.14", /* gpmc_ad10.lcd_data21 */
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"P8.13", /* gpmc_ad9.lcd_data22 */
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"P8.19", /* gpmc_ad8.lcd_data23 */
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"P8.27", /* lcd: LCD_VSYNC : Vertical Sync*/
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"P8.29", /* lcd: LCD_HSYNC : Horizontal Sync */
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"P8.28", /* lcd: LCD_PCLK : Pixel Clock*/
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"P8.30", /* lcd: LCD_AC_BIAS_EN : Used for Display Enable (DE) */
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"P9.14", /* EHRPWM1A: LED Backlight Anode */
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"lcd",
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"ehrpwm1a";
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/* Free all reserved pins from pinmux helpers to ensure they're available */
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fragment@0 {
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target = <&ocp>;
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__overlay__ {
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P9_14_pinmux { status = "disabled"; };
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P8_45_pinmux { status = "disabled"; };
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P8_46_pinmux { status = "disabled"; };
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P8_43_pinmux { status = "disabled"; };
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P8_44_pinmux { status = "disabled"; };
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P8_41_pinmux { status = "disabled"; };
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P8_42_pinmux { status = "disabled"; };
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P8_39_pinmux { status = "disabled"; };
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P8_40_pinmux { status = "disabled"; };
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P8_37_pinmux { status = "disabled"; };
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P8_38_pinmux { status = "disabled"; };
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P8_36_pinmux { status = "disabled"; };
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P8_34_pinmux { status = "disabled"; };
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P8_35_pinmux { status = "disabled"; };
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P8_33_pinmux { status = "disabled"; };
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P8_31_pinmux { status = "disabled"; };
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P8_32_pinmux { status = "disabled"; };
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P8_15_pinmux { status = "disabled"; }; /* gpmc_ad15.lcd_data16 */
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P8_16_pinmux { status = "disabled"; }; /* gpmc_ad14.lcd_data17 */
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P8_11_pinmux { status = "disabled"; }; /* gpmc_ad13.lcd_data18 */
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P8_12_pinmux { status = "disabled"; }; /* gpmc_ad12.lcd_data19 */
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P8_17_pinmux { status = "disabled"; }; /* gpmc_ad11.lcd_data20 */
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P8_14_pinmux { status = "disabled"; }; /* gpmc_ad10.lcd_data21 */
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P8_13_pinmux { status = "disabled"; }; /* gpmc_ad9.lcd_data22 */
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P8_19_pinmux { status = "disabled"; }; /* gpmc_ad8.lcd_data23 */
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P8_27_pinmux { status = "disabled"; };
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P8_29_pinmux { status = "disabled"; };
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P8_28_pinmux { status = "disabled"; };
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P8_30_pinmux { status = "disabled"; };
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};
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};
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/* Assign LCDC pins - Everything is MODE0 output */
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fragment@1 {
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target = <&am33xx_pinmux>;
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__overlay__ {
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pwm_bl_pins: pinmux_pwm_bl_pins {
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pinctrl-single,pins = <
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BONE_P9_14 (PIN_OUTPUT_PULLDOWN | MUX_MODE6) /* P9_14: gpmc_a2.ehrpwm1a */
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>;
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};
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spi0_pins_s0: pinmux_spi0_pins_s0 {
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pinctrl-single,pins = <
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0x150 0x30 /* SPI0_SCLK | MODE0 | INPUT_PULLUP */
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0x154 0x30 /* SPI0_D0 | MODE0 | INPUT_PULLUP */
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0x158 0x10 /* SPI0_D1 | MODE0 | OUTPUT_PULLUP */
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0x15c 0x10 /* SPI0_CS0 | MODE0 | OUTPUT_PULLUP */
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>;
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};
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ve_lcd_pins: pinmux_ve_lcd_pins {
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pinctrl-single,pins = <
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BONE_P8_45 (PIN_OUTPUT | MUX_MODE0) /* LCD_DATA0 | MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
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BONE_P8_46 (PIN_OUTPUT | MUX_MODE0) /* LCD_DATA1 | MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
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BONE_P8_43 (PIN_OUTPUT | MUX_MODE0) /* LCD_DATA2 | MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
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BONE_P8_44 (PIN_OUTPUT | MUX_MODE0) /* LCD_DATA3 | MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
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BONE_P8_41 (PIN_OUTPUT | MUX_MODE0) /* LCD_DATA4 | MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
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BONE_P8_42 (PIN_OUTPUT | MUX_MODE0) /* LCD_DATA5 | MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
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BONE_P8_39 (PIN_OUTPUT | MUX_MODE0) /* LCD_DATA6 | MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
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BONE_P8_40 (PIN_OUTPUT | MUX_MODE0) /* LCD_DATA7 | MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
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BONE_P8_37 (PIN_OUTPUT | MUX_MODE0) /* LCD_DATA8 | MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
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BONE_P8_38 (PIN_OUTPUT | MUX_MODE0) /* LCD_DATA9 | MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
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BONE_P8_36 (PIN_OUTPUT | MUX_MODE0) /* LCD_DATA10 | MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
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BONE_P8_34 (PIN_OUTPUT | MUX_MODE0) /* LCD_DATA11 | MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
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BONE_P8_35 (PIN_OUTPUT | MUX_MODE0) /* LCD_DATA12 | MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
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BONE_P8_33 (PIN_OUTPUT | MUX_MODE0) /* LCD_DATA13 | MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
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BONE_P8_31 (PIN_OUTPUT | MUX_MODE0) /* LCD_DATA14 | MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
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BONE_P8_32 (PIN_OUTPUT | MUX_MODE0) /* LCD_DATA15 | MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
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BONE_P8_15 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad15.lcd_data16 */
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BONE_P8_16 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad14.lcd_data17 */
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BONE_P8_11 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad13.lcd_data18 */
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BONE_P8_12 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad12.lcd_data19 */
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BONE_P8_17 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad11.lcd_data20 */
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BONE_P8_14 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad10.lcd_data21 */
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BONE_P8_13 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad9.lcd_data22 */
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BONE_P8_19 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad8.lcd_data23 */
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BONE_P8_27 (PIN_OUTPUT | MUX_MODE0) /* LCD_VSYNC | MODE0 | AM33XX_PIN_OUTPUT */
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BONE_P8_29 (PIN_OUTPUT | MUX_MODE0) /* LCD_HSYNC | MODE0 | AM33XX_PIN_OUTPUT */
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BONE_P8_28 (PIN_OUTPUT | MUX_MODE0) /* LCD_PCLK | MODE0 | AM33XX_PIN_OUTPUT */
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BONE_P8_30 (PIN_OUTPUT | MUX_MODE0) /* LCD_AC_BIAS_EN | MODE0 | AM33XX_PIN_OUTPUT */
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>;
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};
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};
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};
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fragment@2 {
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target = <&spi0>;
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__overlay__ {
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#address-cells = <1>;
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#size-cells = <0>;
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&spi0_pins_s0>;
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spidev@0 {
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spi-max-frequency = <24000000>;
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reg = <0>;
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compatible = "linux,spidev";
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};
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};
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};
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fragment@3 {
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target = <&lcdc>;
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__overlay__ {
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status = "okay";
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blue-and-red-wiring = "crossed";
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};
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};
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fragment@4 {
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target = <&epwmss1>;
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__overlay__ {
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status = "okay";
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};
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};
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fragment@5 {
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target = <&ehrpwm1>;
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__overlay__ {
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pinctrl-names = "default";
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pinctrl-0 = <&pwm_bl_pins>;
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status = "okay";
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};
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};
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fragment@6 {
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target-path = "/";
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__overlay__ {
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/* avoid stupid warning */
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#address-cells = <1>;
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#size-cells = <1>;
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// backlight {
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// status = "okay";
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// compatible = "pwm-backlight";
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// pwms = <&ehrpwm1 0 250000 0>;
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// brightness-levels = <
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// 0 1 2 3 4 5 6 7 8 9
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// 10 11 12 13 14 15 16 17 18 19
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// 20 21 22 23 24 25 26 27 28 29
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// 30 31 32 33 34 35 36 37 38 39
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// 40 41 42 43 44 45 46 47 48 49
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// 50 51 52 53 54 55 56 57 58 59
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// 60 61 62 63 64 65 66 67 68 69
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// 70 71 72 73 74 75 76 77 78 79
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// 80 81 82 83 84 85 86 87 88 89
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// 90 91 92 93 94 95 96 97 98 99
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// 100
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// >;
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// default-brightness-level = <100>;
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// };
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panel {
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status = "okay";
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compatible = "tilcdc,panel";
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pinctrl-names = "default";
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pinctrl-0 = <&ve_lcd_pins>;
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panel-info {
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ac-bias = <255>; // AC Bias Pin Frequency
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ac-bias-intrpt = <0>; // AC Bias Pin Transitions per Interrupt
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dma-burst-sz = <16>; // DMA burst size
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bpp = <16>; // Bits per pixel (Use 24bpp for 18-bit LCDs)
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fdd = <0x80>; // FIFO DMA Request Delay
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sync-edge = <0>; // Horizontal and Vertical Sync Edge: 0=rising 1=falling
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sync-ctrl = <1>; // Horizontal and Vertical Sync: Control: 0=ignore
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raster-order = <0>; // Raster Data Order Select: 1=Most-to-least 0=Least-to-most
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fifo-th = <0>; // DMA FIFO threshold
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enable-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
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// tft-alt-mode = <0>;
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// stn-565-mode = <0>;
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// mono-8bit-mode = <0>;
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// invert-pxl-clk; // WRONG, DON'T USE
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};
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// typical videomode of lcd panel. Multiple video modes
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// can be listed if the panel supports multiple timings, but the 'native-mode'
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// should be the preferred/default resolution. Refer to
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// Documentation/devicetree/bindings/display/panel/display-timing.txt for display
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// timing binding details.
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display-timings {
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native-mode = <&timing4>;
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timing0: 480x480_TDO {
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clock-frequency = <16000000>; // 60fps
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hactive = <480>;
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vactive = <480>;
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hfront-porch = <24>; //Min: 1; Max: ?; Clock cycles.
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hsync-len = <6>; //Min: 1; Max: 255; Clock cycles.
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hback-porch = <18>; //Min: 1; Max: 255; Clock cycles.
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vfront-porch = <16>; //Min: 2; Max: ?; Lines.
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vsync-len = <4>; //Min: 1; Max: 254; Lines.
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vback-porch = <10>; //Min: 1; Max: 254; Lines.
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hsync-active = <0>;
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vsync-active = <0>;
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de-active = <1>;
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pixelclk-active = <1>;
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};
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timing1: linux_kernel {
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clock-frequency = <27500000>; // 60fps
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hactive = <480>;
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vactive = <854>;
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hfront-porch = <38>;
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hsync-len = <12>;
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hback-porch = <12>;
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vfront-porch = <18>;
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vsync-len = <8>;
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vback-porch = <4>;
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hsync-active = <0>;
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vsync-active = <0>;
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de-active = <1>;
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pixelclk-active = <1>;
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};
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timing3: 480x480_CVT {
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clock-frequency = <17000000>; // 60fps
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hactive = <480>;
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vactive = <480>;
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hfront-porch = <8>;
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hsync-len = <48>;
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hback-porch = <56>;
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vfront-porch = <1>;
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vsync-len = <3>;
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vback-porch = <13>;
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hsync-active = <0>;
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vsync-active = <0>;
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de-active = <1>;
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pixelclk-active = <1>;
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};
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timing4: 640x480_CVT_RB {
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clock-frequency = <23500000>; // 60fps
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hactive = <640>;
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vactive = <480>;
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hfront-porch = <8>;
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hsync-len = <32>;
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hback-porch = <40>;
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vfront-porch = <14>;
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vsync-len = <3>;
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vback-porch = <4>;
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hsync-active = <0>;
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vsync-active = <0>;
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de-active = <1>;
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pixelclk-active = <1>;
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};
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};
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};
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fb {
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compatible = "ti,am33xx-tilcdc";
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reg = <0x4830e000 0x1000>;
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interrupt-parent = <&intc>;
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interrupts = <36>;
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ti,hwmods = "lcdc";
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ti,allow-non-reduced-blanking-modes;
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};
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};
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};
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};
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108
platforms/beaglebone/dt-bindings/board/am335x-bbw-bbb-base.h
Executable file
108
platforms/beaglebone/dt-bindings/board/am335x-bbw-bbb-base.h
Executable file
@ -0,0 +1,108 @@
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/*
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* This header provides constants for bbw/bbb pinctrl bindings.
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*
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* Copyright (C) 2014 Robert Nelson <robertcnelson@gmail.com>
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*
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* Numbers Based on: https://github.com/derekmolloy/boneDeviceTree/tree/master/docs
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*/
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#ifndef _DT_BINDINGS_BOARD_AM335X_BBW_BBB_BASE_H
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#define _DT_BINDINGS_BOARD_AM335X_BBW_BBB_BASE_H
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#define BONE_P8_03 0x018
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#define BONE_P8_04 0x01C
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#define BONE_P8_05 0x008
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#define BONE_P8_06 0x00C
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#define BONE_P8_07 0x090
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#define BONE_P8_08 0x094
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#define BONE_P8_09 0x09C
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#define BONE_P8_10 0x098
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#define BONE_P8_11 0x034
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#define BONE_P8_12 0x030
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#define BONE_P8_13 0x024
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#define BONE_P8_14 0x028
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#define BONE_P8_15 0x03C
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#define BONE_P8_16 0x038
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#define BONE_P8_17 0x02C
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#define BONE_P8_18 0x08C
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#define BONE_P8_19 0x020
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#define BONE_P8_20 0x084
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#define BONE_P8_21 0x080
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#define BONE_P8_22 0x014
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#define BONE_P8_23 0x010
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#define BONE_P8_24 0x004
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#define BONE_P8_25 0x000
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#define BONE_P8_26 0x07C
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#define BONE_P8_27 0x0E0
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#define BONE_P8_28 0x0E8
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#define BONE_P8_29 0x0E4
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#define BONE_P8_30 0x0EC
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#define BONE_P8_31 0x0D8
|
||||
#define BONE_P8_32 0x0DC
|
||||
|
||||
#define BONE_P8_33 0x0D4
|
||||
#define BONE_P8_34 0x0CC
|
||||
#define BONE_P8_35 0x0D0
|
||||
#define BONE_P8_36 0x0C8
|
||||
|
||||
#define BONE_P8_37 0x0C0
|
||||
#define BONE_P8_38 0x0C4
|
||||
#define BONE_P8_39 0x0B8
|
||||
#define BONE_P8_40 0x0BC
|
||||
|
||||
#define BONE_P8_41 0x0B0
|
||||
#define BONE_P8_42 0x0B4
|
||||
#define BONE_P8_43 0x0A8
|
||||
#define BONE_P8_44 0x0AC
|
||||
|
||||
#define BONE_P8_45 0x0A0
|
||||
#define BONE_P8_46 0x0A4
|
||||
|
||||
#define BONE_P9_11 0x070
|
||||
#define BONE_P9_12 0x078
|
||||
|
||||
#define BONE_P9_13 0x074
|
||||
#define BONE_P9_14 0x048
|
||||
#define BONE_P9_15 0x040
|
||||
#define BONE_P9_16 0x04C
|
||||
|
||||
#define BONE_P9_17 0x15C
|
||||
#define BONE_P9_18 0x158
|
||||
#define BONE_P9_19 0x17C
|
||||
#define BONE_P9_20 0x178
|
||||
|
||||
#define BONE_P9_21 0x154
|
||||
#define BONE_P9_22 0x150
|
||||
#define BONE_P9_23 0x044
|
||||
#define BONE_P9_24 0x184
|
||||
|
||||
#define BONE_P9_25 0x1AC
|
||||
#define BONE_P9_26 0x180
|
||||
#define BONE_P9_27 0x1A4
|
||||
#define BONE_P9_28 0x19C
|
||||
|
||||
#define BONE_P9_29 0x194
|
||||
#define BONE_P9_30 0x198
|
||||
#define BONE_P9_31 0x190
|
||||
|
||||
/* Shared P21 of P11 */
|
||||
#define BONE_P9_41 0x1B4
|
||||
#define BONE_P9_41A 0x1B4
|
||||
#define BONE_P9_41B 0x1A8
|
||||
#define BONE_P9_91 0x1A8
|
||||
|
||||
/* Shared P22 of P11 */
|
||||
#define BONE_P9_42 0x164
|
||||
#define BONE_P9_42A 0x164
|
||||
#define BONE_P9_42B 0x1A0
|
||||
#define BONE_P9_92 0x1A0
|
||||
|
||||
#endif
|
||||
|
||||
207
platforms/beaglebone/dt-bindings/board/am335x-pb-base.h
Executable file
207
platforms/beaglebone/dt-bindings/board/am335x-pb-base.h
Executable file
@ -0,0 +1,207 @@
|
||||
/*
|
||||
* This header provides constants for PocketBeagle pinctrl bindings.
|
||||
*
|
||||
* Copyright (C) 2019 Jason Kridner <jdk@ti.com>
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_BOARD_AM335X_PB_BASE_H
|
||||
#define _DT_BINDINGS_BOARD_AM335X_PB_BASE_H
|
||||
|
||||
|
||||
/************************/
|
||||
/* P1 Header */
|
||||
/************************/
|
||||
|
||||
/* P1_01 VIN-AC */
|
||||
|
||||
/* P1_02 (ZCZ ball R5) gpio2_23 */
|
||||
#define PB_P1_02 0x08e4
|
||||
|
||||
/* P1_03 (ZCZ ball F15) usb1_vbus_out */
|
||||
|
||||
/* P1_04 (ZCZ ball R6) gpio2_25 */
|
||||
|
||||
#define PB_P1_04 0x08ec
|
||||
/* P1_05 (ZCZ ball T18) usb1_vbus_in */
|
||||
|
||||
/* P1_06 (ZCZ ball A16) spi0_cs0 */
|
||||
#define PB_P1_06 0x095c
|
||||
|
||||
/* P1_07 VIN-USB */
|
||||
|
||||
/* P1_08 (ZCZ ball A17) spi0_sclk */
|
||||
|
||||
#define PB_P1_08 0x0950
|
||||
/* P1_09 (ZCZ ball R18) USB1-DN */
|
||||
|
||||
/* P1_10 (ZCZ ball B17) spi0_d0 */
|
||||
#define PB_P1_10 0x0954
|
||||
|
||||
/* P1_11 (ZCZ ball R17) USB1-DP */
|
||||
|
||||
/* P1_12 (ZCZ ball B16) spi0_d1 */
|
||||
#define PB_P1_12 0x0958
|
||||
|
||||
/* P1_13 (ZCZ ball P17) USB1-ID */
|
||||
|
||||
/* P1_14 VOUT-3.3V */
|
||||
|
||||
/* P1_15 GND */
|
||||
|
||||
/* P1_16 GND */
|
||||
|
||||
/* P1_17 (ZCZ ball A9) VREFN */
|
||||
|
||||
/* P1_18 (ZCZ ball B9) VREFP */
|
||||
|
||||
/* P1_19 (ZCZ ball B6) AIN0 */
|
||||
|
||||
/* P1_20 (ZCZ ball D14) gpio0_20 */
|
||||
#define PB_P1_20 0x09b4
|
||||
|
||||
/* P1_21 (ZCZ ball C7) AIN1 */
|
||||
|
||||
/* P1_22 GND */
|
||||
|
||||
/* P1_23 (ZCZ ball B7) AIN2 */
|
||||
|
||||
/* P1_24 VOUT-5V */
|
||||
|
||||
/* P1_25 (ZCZ ball A7) AIN3 */
|
||||
|
||||
/* P1_26 (ZCZ ball D18) i2c2_sda */
|
||||
#define PB_P1_26 0x0978
|
||||
|
||||
/* P1_27 (ZCZ ball C8) AIN4 */
|
||||
|
||||
/* P1_28 (ZCZ ball D17) i2c2_scl */
|
||||
#define PB_P1_28 0x097c
|
||||
|
||||
/* P1_29 (ZCZ ball A14) pru0_in7 */
|
||||
#define PB_P1_29 0x09ac
|
||||
|
||||
/* P1_30 (ZCZ ball E16) uart0_txd */
|
||||
#define PB_P1_30 0x0974
|
||||
|
||||
/* P1_31 (ZCZ ball B12) pru0_in4 */
|
||||
#define PB_P1_31 0x09a0
|
||||
|
||||
/* P1_32 (ZCZ ball E15) uart0_rxd */
|
||||
#define PB_P1_32 0x0970
|
||||
|
||||
/* P1_33 (ZCZ ball B13) pru0_in1 */
|
||||
#define PB_P1_33 0x0994
|
||||
|
||||
/* P1_34 (ZCZ ball T11) gpio0_26 */
|
||||
#define PB_P1_34 0x0828
|
||||
|
||||
/* P1_35 (ZCZ ball V5) pru1_in10 */
|
||||
#define PB_P1_35 0x08e8
|
||||
|
||||
/* P1_36 (ZCZ ball A13) ehrpwm0a */
|
||||
#define PB_P1_36 0x0990
|
||||
|
||||
|
||||
/************************/
|
||||
/* P2 Header */
|
||||
/************************/
|
||||
|
||||
/* P2_01 (ZCZ ball U14) ehrpwm1a */
|
||||
#define PB_P2_01 0x0848
|
||||
|
||||
/* P2_02 (ZCZ ball V17) gpio1_27 */
|
||||
#define PB_P2_02 0x086c
|
||||
|
||||
/* P2_03 (ZCZ ball T10) gpio0_23 */
|
||||
#define PB_P2_03 0x0824
|
||||
|
||||
/* P2_04 (ZCZ ball T16) gpio1_26 */
|
||||
#define PB_P2_04 0x0868
|
||||
|
||||
/* P2_05 (ZCZ ball T17) uart4_rxd */
|
||||
#define PB_P2_05 0x0870
|
||||
|
||||
/* P2_06 (ZCZ ball U16) gpio1_25 */
|
||||
#define PB_P2_06 0x0864
|
||||
|
||||
/* P2_07 (ZCZ ball U17) uart4_txd */
|
||||
#define PB_P2_07 0x0874
|
||||
|
||||
/* P2_08 (ZCZ ball U18) gpio1_28 */
|
||||
#define PB_P2_08 0x0878
|
||||
|
||||
/* P2_09 (ZCZ ball D15) i2c1_scl */
|
||||
#define PB_P2_09 0x0984
|
||||
|
||||
/* P2_10 (ZCZ ball R14) gpio1_20 */
|
||||
#define PB_P2_10 0x0850
|
||||
|
||||
/* P2_11 (ZCZ ball D16) i2c1_sda */
|
||||
#define PB_P2_11 0x0980
|
||||
|
||||
/* P2_12 POWER_BUTTON */
|
||||
|
||||
/* P2_13 VOUT-5V */
|
||||
|
||||
/* P2_14 BAT-VIN */
|
||||
|
||||
/* P2_15 GND */
|
||||
|
||||
/* P2_16 BAT-TEMP */
|
||||
|
||||
/* P2_17 (ZCZ ball V12) gpio2_1 */
|
||||
#define PB_P2_17 0x088c
|
||||
|
||||
/* P2_18 (ZCZ ball U13) gpio1_15 */
|
||||
#define PB_P2_18 0x083c
|
||||
|
||||
/* P2_19 (ZCZ ball U12) gpio0_27 */
|
||||
#define PB_P2_19 0x082c
|
||||
|
||||
/* P2_20 (ZCZ ball T13) gpio2_0 */
|
||||
#define PB_P2_20 0x0888
|
||||
|
||||
/* P2_21 GND */
|
||||
|
||||
/* P2_22 (ZCZ ball V13) gpio1_14 */
|
||||
#define PB_P2_22 0x0838
|
||||
|
||||
/* P2_23 VOUT-3.3V */
|
||||
|
||||
/* P2_24 (ZCZ ball T12) gpio1_12 */
|
||||
#define PB_P2_24 0x0830
|
||||
|
||||
/* P2_25 (ZCZ ball E17) spi1_d1 */
|
||||
#define PB_P2_25 0x096c
|
||||
|
||||
/* P2_26 RESET# */
|
||||
|
||||
/* P2_27 (ZCZ ball E18) spi1_d0 */
|
||||
#define PB_P2_27 0x0968
|
||||
|
||||
/* P2_28 (ZCZ ball D13) pru0_in6 */
|
||||
#define PB_P2_28 0x09a8
|
||||
|
||||
/* P2_29 (ZCZ ball C18) spi1_sclk */
|
||||
#define PB_P2_29 0x0964
|
||||
|
||||
/* P2_30 (ZCZ ball C12) pru0_in3 */
|
||||
#define PB_P2_30 0x099c
|
||||
|
||||
/* P2_31 (ZCZ ball A15) spi1_cs1 */
|
||||
#define PB_P2_31 0x09b0
|
||||
|
||||
/* P2_32 (ZCZ ball D12) pru0_in2 */
|
||||
#define PB_P2_32 0x0998
|
||||
|
||||
/* P2_33 (ZCZ ball R12) gpio1_13 */
|
||||
#define PB_P2_33 0x0834
|
||||
|
||||
/* P2_34 (ZCZ ball C13) pru0_in5 */
|
||||
#define PB_P2_34 0x09a4
|
||||
|
||||
/* P2_35 (ZCZ ball U5) gpio2_22 */
|
||||
#define PB_P2_35 0x08e0
|
||||
|
||||
/* P2_36 (ZCZ ball C9) AIN7 */
|
||||
#endif
|
||||
8
platforms/beaglebone/dt-bindings/display/tda998x.h
Executable file
8
platforms/beaglebone/dt-bindings/display/tda998x.h
Executable file
@ -0,0 +1,8 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef _DT_BINDINGS_TDA998X_H
|
||||
#define _DT_BINDINGS_TDA998X_H
|
||||
|
||||
#define TDA998x_SPDIF 1
|
||||
#define TDA998x_I2S 2
|
||||
|
||||
#endif /*_DT_BINDINGS_TDA998X_H */
|
||||
42
platforms/beaglebone/dt-bindings/gpio/gpio.h
Executable file
42
platforms/beaglebone/dt-bindings/gpio/gpio.h
Executable file
@ -0,0 +1,42 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* This header provides constants for most GPIO bindings.
|
||||
*
|
||||
* Most GPIO bindings include a flags cell as part of the GPIO specifier.
|
||||
* In most cases, the format of the flags cell uses the standard values
|
||||
* defined in this header.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_GPIO_GPIO_H
|
||||
#define _DT_BINDINGS_GPIO_GPIO_H
|
||||
|
||||
/* Bit 0 express polarity */
|
||||
#define GPIO_ACTIVE_HIGH 0
|
||||
#define GPIO_ACTIVE_LOW 1
|
||||
|
||||
/* Bit 1 express single-endedness */
|
||||
#define GPIO_PUSH_PULL 0
|
||||
#define GPIO_SINGLE_ENDED 2
|
||||
|
||||
/* Bit 2 express Open drain or open source */
|
||||
#define GPIO_LINE_OPEN_SOURCE 0
|
||||
#define GPIO_LINE_OPEN_DRAIN 4
|
||||
|
||||
/*
|
||||
* Open Drain/Collector is the combination of single-ended open drain interface.
|
||||
* Open Source/Emitter is the combination of single-ended open source interface.
|
||||
*/
|
||||
#define GPIO_OPEN_DRAIN (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_DRAIN)
|
||||
#define GPIO_OPEN_SOURCE (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_SOURCE)
|
||||
|
||||
/* Bit 3 express GPIO suspend/resume and reset persistence */
|
||||
#define GPIO_PERSISTENT 0
|
||||
#define GPIO_TRANSITORY 8
|
||||
|
||||
/* Bit 4 express pull up */
|
||||
#define GPIO_PULL_UP 16
|
||||
|
||||
/* Bit 5 express pull down */
|
||||
#define GPIO_PULL_DOWN 32
|
||||
|
||||
#endif
|
||||
20
platforms/beaglebone/dt-bindings/interrupt-controller/irq.h
Executable file
20
platforms/beaglebone/dt-bindings/interrupt-controller/irq.h
Executable file
@ -0,0 +1,20 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 OR MIT */
|
||||
/*
|
||||
* This header provides constants for most IRQ bindings.
|
||||
*
|
||||
* Most IRQ bindings include a flags cell as part of the IRQ specifier.
|
||||
* In most cases, the format of the flags cell uses the standard values
|
||||
* defined in this header.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H
|
||||
#define _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H
|
||||
|
||||
#define IRQ_TYPE_NONE 0
|
||||
#define IRQ_TYPE_EDGE_RISING 1
|
||||
#define IRQ_TYPE_EDGE_FALLING 2
|
||||
#define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)
|
||||
#define IRQ_TYPE_LEVEL_HIGH 4
|
||||
#define IRQ_TYPE_LEVEL_LOW 8
|
||||
|
||||
#endif
|
||||
172
platforms/beaglebone/dt-bindings/pinctrl/am33xx.h
Executable file
172
platforms/beaglebone/dt-bindings/pinctrl/am33xx.h
Executable file
@ -0,0 +1,172 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* This header provides constants specific to AM33XX pinctrl bindings.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_PINCTRL_AM33XX_H
|
||||
#define _DT_BINDINGS_PINCTRL_AM33XX_H
|
||||
|
||||
#include <dt-bindings/pinctrl/omap.h>
|
||||
|
||||
/* am33xx specific mux bit defines */
|
||||
#undef PULL_ENA
|
||||
#undef INPUT_EN
|
||||
|
||||
#define PULL_DISABLE (1 << 3)
|
||||
#define INPUT_EN (1 << 5)
|
||||
#define SLEWCTRL_SLOW (1 << 6)
|
||||
#define SLEWCTRL_FAST 0
|
||||
|
||||
/* update macro depending on INPUT_EN and PULL_ENA */
|
||||
#undef PIN_OUTPUT
|
||||
#undef PIN_OUTPUT_PULLUP
|
||||
#undef PIN_OUTPUT_PULLDOWN
|
||||
#undef PIN_INPUT
|
||||
#undef PIN_INPUT_PULLUP
|
||||
#undef PIN_INPUT_PULLDOWN
|
||||
|
||||
#define PIN_OUTPUT (PULL_DISABLE)
|
||||
#define PIN_OUTPUT_PULLUP (PULL_UP)
|
||||
#define PIN_OUTPUT_PULLDOWN 0
|
||||
#define PIN_INPUT (INPUT_EN | PULL_DISABLE)
|
||||
#define PIN_INPUT_PULLUP (INPUT_EN | PULL_UP)
|
||||
#define PIN_INPUT_PULLDOWN (INPUT_EN)
|
||||
|
||||
/* undef non-existing modes */
|
||||
#undef PIN_OFF_NONE
|
||||
#undef PIN_OFF_OUTPUT_HIGH
|
||||
#undef PIN_OFF_OUTPUT_LOW
|
||||
#undef PIN_OFF_INPUT_PULLUP
|
||||
#undef PIN_OFF_INPUT_PULLDOWN
|
||||
#undef PIN_OFF_WAKEUPENABLE
|
||||
|
||||
#define AM335X_PIN_OFFSET_MIN 0x0800U
|
||||
|
||||
#define AM335X_PIN_GPMC_AD0 0x800
|
||||
#define AM335X_PIN_GPMC_AD1 0x804
|
||||
#define AM335X_PIN_GPMC_AD2 0x808
|
||||
#define AM335X_PIN_GPMC_AD3 0x80c
|
||||
#define AM335X_PIN_GPMC_AD4 0x810
|
||||
#define AM335X_PIN_GPMC_AD5 0x814
|
||||
#define AM335X_PIN_GPMC_AD6 0x818
|
||||
#define AM335X_PIN_GPMC_AD7 0x81c
|
||||
#define AM335X_PIN_GPMC_AD8 0x820
|
||||
#define AM335X_PIN_GPMC_AD9 0x824
|
||||
#define AM335X_PIN_GPMC_AD10 0x828
|
||||
#define AM335X_PIN_GPMC_AD11 0x82c
|
||||
#define AM335X_PIN_GPMC_AD12 0x830
|
||||
#define AM335X_PIN_GPMC_AD13 0x834
|
||||
#define AM335X_PIN_GPMC_AD14 0x838
|
||||
#define AM335X_PIN_GPMC_AD15 0x83c
|
||||
#define AM335X_PIN_GPMC_A0 0x840
|
||||
#define AM335X_PIN_GPMC_A1 0x844
|
||||
#define AM335X_PIN_GPMC_A2 0x848
|
||||
#define AM335X_PIN_GPMC_A3 0x84c
|
||||
#define AM335X_PIN_GPMC_A4 0x850
|
||||
#define AM335X_PIN_GPMC_A5 0x854
|
||||
#define AM335X_PIN_GPMC_A6 0x858
|
||||
#define AM335X_PIN_GPMC_A7 0x85c
|
||||
#define AM335X_PIN_GPMC_A8 0x860
|
||||
#define AM335X_PIN_GPMC_A9 0x864
|
||||
#define AM335X_PIN_GPMC_A10 0x868
|
||||
#define AM335X_PIN_GPMC_A11 0x86c
|
||||
#define AM335X_PIN_GPMC_WAIT0 0x870
|
||||
#define AM335X_PIN_GPMC_WPN 0x874
|
||||
#define AM335X_PIN_GPMC_BEN1 0x878
|
||||
#define AM335X_PIN_GPMC_CSN0 0x87c
|
||||
#define AM335X_PIN_GPMC_CSN1 0x880
|
||||
#define AM335X_PIN_GPMC_CSN2 0x884
|
||||
#define AM335X_PIN_GPMC_CSN3 0x888
|
||||
#define AM335X_PIN_GPMC_CLK 0x88c
|
||||
#define AM335X_PIN_GPMC_ADVN_ALE 0x890
|
||||
#define AM335X_PIN_GPMC_OEN_REN 0x894
|
||||
#define AM335X_PIN_GPMC_WEN 0x898
|
||||
#define AM335X_PIN_GPMC_BEN0_CLE 0x89c
|
||||
#define AM335X_PIN_LCD_DATA0 0x8a0
|
||||
#define AM335X_PIN_LCD_DATA1 0x8a4
|
||||
#define AM335X_PIN_LCD_DATA2 0x8a8
|
||||
#define AM335X_PIN_LCD_DATA3 0x8ac
|
||||
#define AM335X_PIN_LCD_DATA4 0x8b0
|
||||
#define AM335X_PIN_LCD_DATA5 0x8b4
|
||||
#define AM335X_PIN_LCD_DATA6 0x8b8
|
||||
#define AM335X_PIN_LCD_DATA7 0x8bc
|
||||
#define AM335X_PIN_LCD_DATA8 0x8c0
|
||||
#define AM335X_PIN_LCD_DATA9 0x8c4
|
||||
#define AM335X_PIN_LCD_DATA10 0x8c8
|
||||
#define AM335X_PIN_LCD_DATA11 0x8cc
|
||||
#define AM335X_PIN_LCD_DATA12 0x8d0
|
||||
#define AM335X_PIN_LCD_DATA13 0x8d4
|
||||
#define AM335X_PIN_LCD_DATA14 0x8d8
|
||||
#define AM335X_PIN_LCD_DATA15 0x8dc
|
||||
#define AM335X_PIN_LCD_VSYNC 0x8e0
|
||||
#define AM335X_PIN_LCD_HSYNC 0x8e4
|
||||
#define AM335X_PIN_LCD_PCLK 0x8e8
|
||||
#define AM335X_PIN_LCD_AC_BIAS_EN 0x8ec
|
||||
#define AM335X_PIN_MMC0_DAT3 0x8f0
|
||||
#define AM335X_PIN_MMC0_DAT2 0x8f4
|
||||
#define AM335X_PIN_MMC0_DAT1 0x8f8
|
||||
#define AM335X_PIN_MMC0_DAT0 0x8fc
|
||||
#define AM335X_PIN_MMC0_CLK 0x900
|
||||
#define AM335X_PIN_MMC0_CMD 0x904
|
||||
#define AM335X_PIN_MII1_COL 0x908
|
||||
#define AM335X_PIN_MII1_CRS 0x90c
|
||||
#define AM335X_PIN_MII1_RX_ER 0x910
|
||||
#define AM335X_PIN_MII1_TX_EN 0x914
|
||||
#define AM335X_PIN_MII1_RX_DV 0x918
|
||||
#define AM335X_PIN_MII1_TXD3 0x91c
|
||||
#define AM335X_PIN_MII1_TXD2 0x920
|
||||
#define AM335X_PIN_MII1_TXD1 0x924
|
||||
#define AM335X_PIN_MII1_TXD0 0x928
|
||||
#define AM335X_PIN_MII1_TX_CLK 0x92c
|
||||
#define AM335X_PIN_MII1_RX_CLK 0x930
|
||||
#define AM335X_PIN_MII1_RXD3 0x934
|
||||
#define AM335X_PIN_MII1_RXD2 0x938
|
||||
#define AM335X_PIN_MII1_RXD1 0x93c
|
||||
#define AM335X_PIN_MII1_RXD0 0x940
|
||||
#define AM335X_PIN_RMII1_REF_CLK 0x944
|
||||
#define AM335X_PIN_MDIO 0x948
|
||||
#define AM335X_PIN_MDC 0x94c
|
||||
#define AM335X_PIN_SPI0_SCLK 0x950
|
||||
#define AM335X_PIN_SPI0_D0 0x954
|
||||
#define AM335X_PIN_SPI0_D1 0x958
|
||||
#define AM335X_PIN_SPI0_CS0 0x95c
|
||||
#define AM335X_PIN_SPI0_CS1 0x960
|
||||
#define AM335X_PIN_ECAP0_IN_PWM0_OUT 0x964
|
||||
#define AM335X_PIN_UART0_CTSN 0x968
|
||||
#define AM335X_PIN_UART0_RTSN 0x96c
|
||||
#define AM335X_PIN_UART0_RXD 0x970
|
||||
#define AM335X_PIN_UART0_TXD 0x974
|
||||
#define AM335X_PIN_UART1_CTSN 0x978
|
||||
#define AM335X_PIN_UART1_RTSN 0x97c
|
||||
#define AM335X_PIN_UART1_RXD 0x980
|
||||
#define AM335X_PIN_UART1_TXD 0x984
|
||||
#define AM335X_PIN_I2C0_SDA 0x988
|
||||
#define AM335X_PIN_I2C0_SCL 0x98c
|
||||
#define AM335X_PIN_MCASP0_ACLKX 0x990
|
||||
#define AM335X_PIN_MCASP0_FSX 0x994
|
||||
#define AM335X_PIN_MCASP0_AXR0 0x998
|
||||
#define AM335X_PIN_MCASP0_AHCLKR 0x99c
|
||||
#define AM335X_PIN_MCASP0_ACLKR 0x9a0
|
||||
#define AM335X_PIN_MCASP0_FSR 0x9a4
|
||||
#define AM335X_PIN_MCASP0_AXR1 0x9a8
|
||||
#define AM335X_PIN_MCASP0_AHCLKX 0x9ac
|
||||
#define AM335X_PIN_XDMA_EVENT_INTR0 0x9b0
|
||||
#define AM335X_PIN_XDMA_EVENT_INTR1 0x9b4
|
||||
#define AM335X_PIN_WARMRSTN 0x9b8
|
||||
#define AM335X_PIN_NNMI 0x9c0
|
||||
#define AM335X_PIN_TMS 0x9d0
|
||||
#define AM335X_PIN_TDI 0x9d4
|
||||
#define AM335X_PIN_TDO 0x9d8
|
||||
#define AM335X_PIN_TCK 0x9dc
|
||||
#define AM335X_PIN_TRSTN 0x9e0
|
||||
#define AM335X_PIN_EMU0 0x9e4
|
||||
#define AM335X_PIN_EMU1 0x9e8
|
||||
#define AM335X_PIN_RTC_PWRONRSTN 0x9f8
|
||||
#define AM335X_PIN_PMIC_POWER_EN 0x9fc
|
||||
#define AM335X_PIN_EXT_WAKEUP 0xa00
|
||||
#define AM335X_PIN_USB0_DRVVBUS 0xa1c
|
||||
#define AM335X_PIN_USB1_DRVVBUS 0xa34
|
||||
|
||||
#define AM335X_PIN_OFFSET_MAX 0x0a34U
|
||||
|
||||
#endif
|
||||
498
platforms/beaglebone/dt-bindings/pinctrl/dra.h
Executable file
498
platforms/beaglebone/dt-bindings/pinctrl/dra.h
Executable file
@ -0,0 +1,498 @@
|
||||
/*
|
||||
* This header provides constants for DRA pinctrl bindings.
|
||||
*
|
||||
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
|
||||
* Author: Rajendra Nayak <rnayak@ti.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_PINCTRL_DRA_H
|
||||
#define _DT_BINDINGS_PINCTRL_DRA_H
|
||||
|
||||
/* DRA7 mux mode options for each pin. See TRM for options */
|
||||
#define MUX_MODE0 0x0
|
||||
#define MUX_MODE1 0x1
|
||||
#define MUX_MODE2 0x2
|
||||
#define MUX_MODE3 0x3
|
||||
#define MUX_MODE4 0x4
|
||||
#define MUX_MODE5 0x5
|
||||
#define MUX_MODE6 0x6
|
||||
#define MUX_MODE7 0x7
|
||||
#define MUX_MODE8 0x8
|
||||
#define MUX_MODE9 0x9
|
||||
#define MUX_MODE10 0xa
|
||||
#define MUX_MODE11 0xb
|
||||
#define MUX_MODE12 0xc
|
||||
#define MUX_MODE13 0xd
|
||||
#define MUX_MODE14 0xe
|
||||
#define MUX_MODE15 0xf
|
||||
|
||||
/* Certain pins need virtual mode, but note: they may glitch */
|
||||
#define MUX_VIRTUAL_MODE0 (MODE_SELECT | (0x0 << 4))
|
||||
#define MUX_VIRTUAL_MODE1 (MODE_SELECT | (0x1 << 4))
|
||||
#define MUX_VIRTUAL_MODE2 (MODE_SELECT | (0x2 << 4))
|
||||
#define MUX_VIRTUAL_MODE3 (MODE_SELECT | (0x3 << 4))
|
||||
#define MUX_VIRTUAL_MODE4 (MODE_SELECT | (0x4 << 4))
|
||||
#define MUX_VIRTUAL_MODE5 (MODE_SELECT | (0x5 << 4))
|
||||
#define MUX_VIRTUAL_MODE6 (MODE_SELECT | (0x6 << 4))
|
||||
#define MUX_VIRTUAL_MODE7 (MODE_SELECT | (0x7 << 4))
|
||||
#define MUX_VIRTUAL_MODE8 (MODE_SELECT | (0x8 << 4))
|
||||
#define MUX_VIRTUAL_MODE9 (MODE_SELECT | (0x9 << 4))
|
||||
#define MUX_VIRTUAL_MODE10 (MODE_SELECT | (0xa << 4))
|
||||
#define MUX_VIRTUAL_MODE11 (MODE_SELECT | (0xb << 4))
|
||||
#define MUX_VIRTUAL_MODE12 (MODE_SELECT | (0xc << 4))
|
||||
#define MUX_VIRTUAL_MODE13 (MODE_SELECT | (0xd << 4))
|
||||
#define MUX_VIRTUAL_MODE14 (MODE_SELECT | (0xe << 4))
|
||||
#define MUX_VIRTUAL_MODE15 (MODE_SELECT | (0xf << 4))
|
||||
|
||||
#define MODE_SELECT (1 << 8)
|
||||
|
||||
#define PULL_ENA (0 << 16)
|
||||
#define PULL_DIS (1 << 16)
|
||||
#define PULL_UP (1 << 17)
|
||||
#define INPUT_EN (1 << 18)
|
||||
#define SLEWCONTROL (1 << 19)
|
||||
#define WAKEUP_EN (1 << 24)
|
||||
#define WAKEUP_EVENT (1 << 25)
|
||||
|
||||
/* Active pin states */
|
||||
#define PIN_OUTPUT (0 | PULL_DIS)
|
||||
#define PIN_OUTPUT_PULLUP (PULL_UP)
|
||||
#define PIN_OUTPUT_PULLDOWN (0)
|
||||
#define PIN_INPUT (INPUT_EN | PULL_DIS)
|
||||
#define PIN_INPUT_SLEW (INPUT_EN | SLEWCONTROL)
|
||||
#define PIN_INPUT_PULLUP (PULL_ENA | INPUT_EN | PULL_UP)
|
||||
#define PIN_INPUT_PULLDOWN (PULL_ENA | INPUT_EN)
|
||||
|
||||
/*
|
||||
* Macro to allow using the absolute physical address instead of the
|
||||
* padconf registers instead of the offset from padconf base.
|
||||
*/
|
||||
#define DRA7XX_CORE_IOPAD(pa, val) (((pa) & 0xffff) - 0x3400) (val)
|
||||
|
||||
/* DRA7 IODELAY configuration parameters */
|
||||
#define A_DELAY_PS(val) ((val) & 0xffff)
|
||||
#define G_DELAY_PS(val) ((val) & 0xffff)
|
||||
|
||||
#define DRA7XX_PIN_OFFSET_MIN 0x3400U
|
||||
|
||||
#define DRA7XX_PIN_GPMC_AD0 0x3400
|
||||
#define DRA7XX_PIN_GPMC_AD1 0x3404
|
||||
#define DRA7XX_PIN_GPMC_AD2 0x3408
|
||||
#define DRA7XX_PIN_GPMC_AD3 0x340C
|
||||
#define DRA7XX_PIN_GPMC_AD4 0x3410
|
||||
#define DRA7XX_PIN_GPMC_AD5 0x3414
|
||||
#define DRA7XX_PIN_GPMC_AD6 0x3418
|
||||
#define DRA7XX_PIN_GPMC_AD7 0x341C
|
||||
#define DRA7XX_PIN_GPMC_AD8 0x3420
|
||||
#define DRA7XX_PIN_GPMC_AD9 0x3424
|
||||
#define DRA7XX_PIN_GPMC_AD10 0x3428
|
||||
#define DRA7XX_PIN_GPMC_AD11 0x342C
|
||||
#define DRA7XX_PIN_GPMC_AD12 0x3430
|
||||
#define DRA7XX_PIN_GPMC_AD13 0x3434
|
||||
#define DRA7XX_PIN_GPMC_AD14 0x3438
|
||||
#define DRA7XX_PIN_GPMC_AD15 0x343C
|
||||
#define DRA7XX_PIN_GPMC_A0 0x3440
|
||||
#define DRA7XX_PIN_GPMC_A1 0x3444
|
||||
#define DRA7XX_PIN_GPMC_A2 0x3448
|
||||
#define DRA7XX_PIN_GPMC_A3 0x344C
|
||||
#define DRA7XX_PIN_GPMC_A4 0x3450
|
||||
#define DRA7XX_PIN_GPMC_A5 0x3454
|
||||
#define DRA7XX_PIN_GPMC_A6 0x3458
|
||||
#define DRA7XX_PIN_GPMC_A7 0x345C
|
||||
#define DRA7XX_PIN_GPMC_A8 0x3460
|
||||
#define DRA7XX_PIN_GPMC_A9 0x3464
|
||||
#define DRA7XX_PIN_GPMC_A10 0x3468
|
||||
#define DRA7XX_PIN_GPMC_A11 0x346C
|
||||
#define DRA7XX_PIN_GPMC_A12 0x3470
|
||||
#define DRA7XX_PIN_GPMC_A13 0x3474
|
||||
#define DRA7XX_PIN_GPMC_A14 0x3478
|
||||
#define DRA7XX_PIN_GPMC_A15 0x347C
|
||||
#define DRA7XX_PIN_GPMC_A16 0x3480
|
||||
#define DRA7XX_PIN_GPMC_A17 0x3484
|
||||
#define DRA7XX_PIN_GPMC_A18 0x3488
|
||||
#define DRA7XX_PIN_GPMC_A19 0x348C
|
||||
#define DRA7XX_PIN_GPMC_A20 0x3490
|
||||
#define DRA7XX_PIN_GPMC_A21 0x3494
|
||||
#define DRA7XX_PIN_GPMC_A22 0x3498
|
||||
#define DRA7XX_PIN_GPMC_A23 0x349C
|
||||
#define DRA7XX_PIN_GPMC_A24 0x34A0
|
||||
#define DRA7XX_PIN_GPMC_A25 0x34A4
|
||||
#define DRA7XX_PIN_GPMC_A26 0x34A8
|
||||
#define DRA7XX_PIN_GPMC_A27 0x34AC
|
||||
#define DRA7XX_PIN_GPMC_CS1 0x34B0
|
||||
#define DRA7XX_PIN_GPMC_CS0 0x34B4
|
||||
#define DRA7XX_PIN_GPMC_CS2 0x34B8
|
||||
#define DRA7XX_PIN_GPMC_CS3 0x34BC
|
||||
#define DRA7XX_PIN_GPMC_CLK 0x34C0
|
||||
#define DRA7XX_PIN_GPMC_ADVN_ALE 0x34C4
|
||||
#define DRA7XX_PIN_GPMC_OEN_REN 0x34C8
|
||||
#define DRA7XX_PIN_GPMC_WEN 0x34CC
|
||||
#define DRA7XX_PIN_GPMC_BEN0 0x34D0
|
||||
#define DRA7XX_PIN_GPMC_BEN1 0x34D4
|
||||
#define DRA7XX_PIN_GPMC_WAIT0 0x34D8
|
||||
#define DRA7XX_PIN_VIN1A_CLK0 0x34DC
|
||||
#define DRA7XX_PIN_VIN1B_CLK1 0x34E0
|
||||
#define DRA7XX_PIN_VIN1A_DE0 0x34E4
|
||||
#define DRA7XX_PIN_VIN1A_FLD0 0x34E8
|
||||
#define DRA7XX_PIN_VIN1A_HSYNC0 0x34EC
|
||||
#define DRA7XX_PIN_VIN1A_VSYNC0 0x34F0
|
||||
#define DRA7XX_PIN_VIN1A_D0 0x34F4
|
||||
#define DRA7XX_PIN_VIN1A_D1 0x34F8
|
||||
#define DRA7XX_PIN_VIN1A_D2 0x34FC
|
||||
#define DRA7XX_PIN_VIN1A_D3 0x3500
|
||||
#define DRA7XX_PIN_VIN1A_D4 0x3504
|
||||
#define DRA7XX_PIN_VIN1A_D5 0x3508
|
||||
#define DRA7XX_PIN_VIN1A_D6 0x350C
|
||||
#define DRA7XX_PIN_VIN1A_D7 0x3510
|
||||
#define DRA7XX_PIN_VIN1A_D8 0x3514
|
||||
#define DRA7XX_PIN_VIN1A_D9 0x3518
|
||||
#define DRA7XX_PIN_VIN1A_D10 0x351C
|
||||
#define DRA7XX_PIN_VIN1A_D11 0x3520
|
||||
#define DRA7XX_PIN_VIN1A_D12 0x3524
|
||||
#define DRA7XX_PIN_VIN1A_D13 0x3528
|
||||
#define DRA7XX_PIN_VIN1A_D14 0x352C
|
||||
#define DRA7XX_PIN_VIN1A_D15 0x3530
|
||||
#define DRA7XX_PIN_VIN1A_D16 0x3534
|
||||
#define DRA7XX_PIN_VIN1A_D17 0x3538
|
||||
#define DRA7XX_PIN_VIN1A_D18 0x353C
|
||||
#define DRA7XX_PIN_VIN1A_D19 0x3540
|
||||
#define DRA7XX_PIN_VIN1A_D20 0x3544
|
||||
#define DRA7XX_PIN_VIN1A_D21 0x3548
|
||||
#define DRA7XX_PIN_VIN1A_D22 0x354C
|
||||
#define DRA7XX_PIN_VIN1A_D23 0x3550
|
||||
#define DRA7XX_PIN_VIN2A_CLK0 0x3554
|
||||
#define DRA7XX_PIN_VIN2A_DE0 0x3558
|
||||
#define DRA7XX_PIN_VIN2A_FLD0 0x355C
|
||||
#define DRA7XX_PIN_VIN2A_HSYNC0 0x3560
|
||||
#define DRA7XX_PIN_VIN2A_VSYNC0 0x3564
|
||||
#define DRA7XX_PIN_VIN2A_D0 0x3568
|
||||
#define DRA7XX_PIN_VIN2A_D1 0x356C
|
||||
#define DRA7XX_PIN_VIN2A_D2 0x3570
|
||||
#define DRA7XX_PIN_VIN2A_D3 0x3574
|
||||
#define DRA7XX_PIN_VIN2A_D4 0x3578
|
||||
#define DRA7XX_PIN_VIN2A_D5 0x357C
|
||||
#define DRA7XX_PIN_VIN2A_D6 0x3580
|
||||
#define DRA7XX_PIN_VIN2A_D7 0x3584
|
||||
#define DRA7XX_PIN_VIN2A_D8 0x3588
|
||||
#define DRA7XX_PIN_VIN2A_D9 0x358C
|
||||
#define DRA7XX_PIN_VIN2A_D10 0x3590
|
||||
#define DRA7XX_PIN_VIN2A_D11 0x3594
|
||||
#define DRA7XX_PIN_VIN2A_D12 0x3598
|
||||
#define DRA7XX_PIN_VIN2A_D13 0x359C
|
||||
#define DRA7XX_PIN_VIN2A_D14 0x35A0
|
||||
#define DRA7XX_PIN_VIN2A_D15 0x35A4
|
||||
#define DRA7XX_PIN_VIN2A_D16 0x35A8
|
||||
#define DRA7XX_PIN_VIN2A_D17 0x35AC
|
||||
#define DRA7XX_PIN_VIN2A_D18 0x35B0
|
||||
#define DRA7XX_PIN_VIN2A_D19 0x35B4
|
||||
#define DRA7XX_PIN_VIN2A_D20 0x35B8
|
||||
#define DRA7XX_PIN_VIN2A_D21 0x35BC
|
||||
#define DRA7XX_PIN_VIN2A_D22 0x35C0
|
||||
#define DRA7XX_PIN_VIN2A_D23 0x35C4
|
||||
#define DRA7XX_PIN_VOUT1_CLK 0x35C8
|
||||
#define DRA7XX_PIN_VOUT1_DE 0x35CC
|
||||
#define DRA7XX_PIN_VOUT1_FLD 0x35D0
|
||||
#define DRA7XX_PIN_VOUT1_HSYNC 0x35D4
|
||||
#define DRA7XX_PIN_VOUT1_VSYNC 0x35D8
|
||||
#define DRA7XX_PIN_VOUT1_D0 0x35DC
|
||||
#define DRA7XX_PIN_VOUT1_D1 0x35E0
|
||||
#define DRA7XX_PIN_VOUT1_D2 0x35E4
|
||||
#define DRA7XX_PIN_VOUT1_D3 0x35E8
|
||||
#define DRA7XX_PIN_VOUT1_D4 0x35EC
|
||||
#define DRA7XX_PIN_VOUT1_D5 0x35F0
|
||||
#define DRA7XX_PIN_VOUT1_D6 0x35F4
|
||||
#define DRA7XX_PIN_VOUT1_D7 0x35F8
|
||||
#define DRA7XX_PIN_VOUT1_D8 0x35FC
|
||||
#define DRA7XX_PIN_VOUT1_D9 0x3600
|
||||
#define DRA7XX_PIN_VOUT1_D10 0x3604
|
||||
#define DRA7XX_PIN_VOUT1_D11 0x3608
|
||||
#define DRA7XX_PIN_VOUT1_D12 0x360C
|
||||
#define DRA7XX_PIN_VOUT1_D13 0x3610
|
||||
#define DRA7XX_PIN_VOUT1_D14 0x3614
|
||||
#define DRA7XX_PIN_VOUT1_D15 0x3618
|
||||
#define DRA7XX_PIN_VOUT1_D16 0x361C
|
||||
#define DRA7XX_PIN_VOUT1_D17 0x3620
|
||||
#define DRA7XX_PIN_VOUT1_D18 0x3624
|
||||
#define DRA7XX_PIN_VOUT1_D19 0x3628
|
||||
#define DRA7XX_PIN_VOUT1_D20 0x362C
|
||||
#define DRA7XX_PIN_VOUT1_D21 0x3630
|
||||
#define DRA7XX_PIN_VOUT1_D22 0x3634
|
||||
#define DRA7XX_PIN_VOUT1_D23 0x3638
|
||||
#define DRA7XX_PIN_MDIO_MCLK 0x363C
|
||||
#define DRA7XX_PIN_MDIO_D 0x3640
|
||||
#define DRA7XX_PIN_RMII_MHZ_50_CLK 0x3644
|
||||
#define DRA7XX_PIN_UART3_RXD 0x3648
|
||||
#define DRA7XX_PIN_UART3_TXD 0x364C
|
||||
#define DRA7XX_PIN_RGMII0_TXC 0x3650
|
||||
#define DRA7XX_PIN_RGMII0_TXCTL 0x3654
|
||||
#define DRA7XX_PIN_RGMII0_TXD3 0x3658
|
||||
#define DRA7XX_PIN_RGMII0_TXD2 0x365C
|
||||
#define DRA7XX_PIN_RGMII0_TXD1 0x3660
|
||||
#define DRA7XX_PIN_RGMII0_TXD0 0x3664
|
||||
#define DRA7XX_PIN_RGMII0_RXC 0x3668
|
||||
#define DRA7XX_PIN_RGMII0_RXCTL 0x366C
|
||||
#define DRA7XX_PIN_RGMII0_RXD3 0x3670
|
||||
#define DRA7XX_PIN_RGMII0_RXD2 0x3674
|
||||
#define DRA7XX_PIN_RGMII0_RXD1 0x3678
|
||||
#define DRA7XX_PIN_RGMII0_RXD0 0x367C
|
||||
#define DRA7XX_PIN_USB1_DRVVBUS 0x3680
|
||||
#define DRA7XX_PIN_USB2_DRVVBUS 0x3684
|
||||
#define DRA7XX_PIN_GPIO6_14 0x3688
|
||||
#define DRA7XX_PIN_GPIO6_15 0x368C
|
||||
#define DRA7XX_PIN_GPIO6_16 0x3690
|
||||
#define DRA7XX_PIN_XREF_CLK0 0x3694
|
||||
#define DRA7XX_PIN_XREF_CLK1 0x3698
|
||||
#define DRA7XX_PIN_XREF_CLK2 0x369C
|
||||
#define DRA7XX_PIN_XREF_CLK3 0x36A0
|
||||
#define DRA7XX_PIN_MCASP1_ACLKX 0x36A4
|
||||
#define DRA7XX_PIN_MCASP1_FSX 0x36A8
|
||||
#define DRA7XX_PIN_MCASP1_ACLKR 0x36AC
|
||||
#define DRA7XX_PIN_MCASP1_FSR 0x36B0
|
||||
#define DRA7XX_PIN_MCASP1_AXR0 0x36B4
|
||||
#define DRA7XX_PIN_MCASP1_AXR1 0x36B8
|
||||
#define DRA7XX_PIN_MCASP1_AXR2 0x36BC
|
||||
#define DRA7XX_PIN_MCASP1_AXR3 0x36C0
|
||||
#define DRA7XX_PIN_MCASP1_AXR4 0x36C4
|
||||
#define DRA7XX_PIN_MCASP1_AXR5 0x36C8
|
||||
#define DRA7XX_PIN_MCASP1_AXR6 0x36CC
|
||||
#define DRA7XX_PIN_MCASP1_AXR7 0x36D0
|
||||
#define DRA7XX_PIN_MCASP1_AXR8 0x36D4
|
||||
#define DRA7XX_PIN_MCASP1_AXR9 0x36D8
|
||||
#define DRA7XX_PIN_MCASP1_AXR10 0x36DC
|
||||
#define DRA7XX_PIN_MCASP1_AXR11 0x36E0
|
||||
#define DRA7XX_PIN_MCASP1_AXR12 0x36E4
|
||||
#define DRA7XX_PIN_MCASP1_AXR13 0x36E8
|
||||
#define DRA7XX_PIN_MCASP1_AXR14 0x36EC
|
||||
#define DRA7XX_PIN_MCASP1_AXR15 0x36F0
|
||||
#define DRA7XX_PIN_MCASP2_ACLKX 0x36F4
|
||||
#define DRA7XX_PIN_MCASP2_FSX 0x36F8
|
||||
#define DRA7XX_PIN_MCASP2_ACLKR 0x36FC
|
||||
#define DRA7XX_PIN_MCASP2_FSR 0x3700
|
||||
#define DRA7XX_PIN_MCASP2_AXR0 0x3704
|
||||
#define DRA7XX_PIN_MCASP2_AXR1 0x3708
|
||||
#define DRA7XX_PIN_MCASP2_AXR2 0x370C
|
||||
#define DRA7XX_PIN_MCASP2_AXR3 0x3710
|
||||
#define DRA7XX_PIN_MCASP2_AXR4 0x3714
|
||||
#define DRA7XX_PIN_MCASP2_AXR5 0x3718
|
||||
#define DRA7XX_PIN_MCASP2_AXR6 0x371C
|
||||
#define DRA7XX_PIN_MCASP2_AXR7 0x3720
|
||||
#define DRA7XX_PIN_MCASP3_ACLKX 0x3724
|
||||
#define DRA7XX_PIN_MCASP3_FSX 0x3728
|
||||
#define DRA7XX_PIN_MCASP3_AXR0 0x372C
|
||||
#define DRA7XX_PIN_MCASP3_AXR1 0x3730
|
||||
#define DRA7XX_PIN_MCASP4_ACLKX 0x3734
|
||||
#define DRA7XX_PIN_MCASP4_FSX 0x3738
|
||||
#define DRA7XX_PIN_MCASP4_AXR0 0x373C
|
||||
#define DRA7XX_PIN_MCASP4_AXR1 0x3740
|
||||
#define DRA7XX_PIN_MCASP5_ACLKX 0x3744
|
||||
#define DRA7XX_PIN_MCASP5_FSX 0x3748
|
||||
#define DRA7XX_PIN_MCASP5_AXR0 0x374C
|
||||
#define DRA7XX_PIN_MCASP5_AXR1 0x3750
|
||||
#define DRA7XX_PIN_MMC1_CLK 0x3754
|
||||
#define DRA7XX_PIN_MMC1_CMD 0x3758
|
||||
#define DRA7XX_PIN_MMC1_DAT0 0x375C
|
||||
#define DRA7XX_PIN_MMC1_DAT1 0x3760
|
||||
#define DRA7XX_PIN_MMC1_DAT2 0x3764
|
||||
#define DRA7XX_PIN_MMC1_DAT3 0x3768
|
||||
#define DRA7XX_PIN_MMC1_SDCD 0x376C
|
||||
#define DRA7XX_PIN_MMC1_SDWP 0x3770
|
||||
#define DRA7XX_PIN_GPIO6_10 0x3774
|
||||
#define DRA7XX_PIN_GPIO6_11 0x3778
|
||||
#define DRA7XX_PIN_MMC3_CLK 0x377C
|
||||
#define DRA7XX_PIN_MMC3_CMD 0x3780
|
||||
#define DRA7XX_PIN_MMC3_DAT0 0x3784
|
||||
#define DRA7XX_PIN_MMC3_DAT1 0x3788
|
||||
#define DRA7XX_PIN_MMC3_DAT2 0x378C
|
||||
#define DRA7XX_PIN_MMC3_DAT3 0x3790
|
||||
#define DRA7XX_PIN_MMC3_DAT4 0x3794
|
||||
#define DRA7XX_PIN_MMC3_DAT5 0x3798
|
||||
#define DRA7XX_PIN_MMC3_DAT6 0x379C
|
||||
#define DRA7XX_PIN_MMC3_DAT7 0x37A0
|
||||
#define DRA7XX_PIN_SPI1_SCLK 0x37A4
|
||||
#define DRA7XX_PIN_SPI1_D1 0x37A8
|
||||
#define DRA7XX_PIN_SPI1_D0 0x37AC
|
||||
#define DRA7XX_PIN_SPI1_CS0 0x37B0
|
||||
#define DRA7XX_PIN_SPI1_CS1 0x37B4
|
||||
#define DRA7XX_PIN_SPI1_CS2 0x37B8
|
||||
#define DRA7XX_PIN_SPI1_CS3 0x37BC
|
||||
#define DRA7XX_PIN_SPI2_SCLK 0x37C0
|
||||
#define DRA7XX_PIN_SPI2_D1 0x37C4
|
||||
#define DRA7XX_PIN_SPI2_D0 0x37C8
|
||||
#define DRA7XX_PIN_SPI2_CS0 0x37CC
|
||||
#define DRA7XX_PIN_DCAN1_TX 0x37D0
|
||||
#define DRA7XX_PIN_DCAN1_RX 0x37D4
|
||||
#define DRA7XX_PIN_UART1_RXD 0x37E0
|
||||
#define DRA7XX_PIN_UART1_TXD 0x37E4
|
||||
#define DRA7XX_PIN_UART1_CTSN 0x37E8
|
||||
#define DRA7XX_PIN_UART1_RTSN 0x37EC
|
||||
#define DRA7XX_PIN_UART2_RXD 0x37F0
|
||||
#define DRA7XX_PIN_UART2_TXD 0x37F4
|
||||
#define DRA7XX_PIN_UART2_CTSN 0x37F8
|
||||
#define DRA7XX_PIN_UART2_RTSN 0x37FC
|
||||
#define DRA7XX_PIN_I2C1_SDA 0x3800
|
||||
#define DRA7XX_PIN_I2C1_SCL 0x3804
|
||||
#define DRA7XX_PIN_I2C2_SDA 0x3808
|
||||
#define DRA7XX_PIN_I2C2_SCL 0x380C
|
||||
#define DRA7XX_PIN_WAKEUP0 0x3818
|
||||
#define DRA7XX_PIN_WAKEUP1 0x381C
|
||||
#define DRA7XX_PIN_WAKEUP2 0x3820
|
||||
#define DRA7XX_PIN_WAKEUP3 0x3824
|
||||
#define DRA7XX_PIN_ON_OFF 0x3828
|
||||
#define DRA7XX_PIN_RTC_PORZ 0x382C
|
||||
#define DRA7XX_PIN_TMS 0x3830
|
||||
#define DRA7XX_PIN_TDI 0x3834
|
||||
#define DRA7XX_PIN_TDO 0x3838
|
||||
#define DRA7XX_PIN_TCLK 0x383C
|
||||
#define DRA7XX_PIN_TRSTN 0x3840
|
||||
#define DRA7XX_PIN_RTCK 0x3844
|
||||
#define DRA7XX_PIN_EMU0 0x3848
|
||||
#define DRA7XX_PIN_EMU1 0x384C
|
||||
#define DRA7XX_PIN_RESETN 0x385C
|
||||
#define DRA7XX_PIN_NMIN_DSP 0x3860
|
||||
#define DRA7XX_PIN_RSTOUTN 0x3864
|
||||
|
||||
#define DRA7XX_PIN_OFFSET_MAX 0x3864U
|
||||
|
||||
/*
|
||||
* https://docs.google.com/spreadsheets/d/1fE-AsDZvJ-bBwzNBj1_sPDrutvEvsmARqFwvbw_HkrE/edit#gid=227990209
|
||||
*/
|
||||
|
||||
#define BBAI_P8_03 DRA7XX_PIN_MMC3_DAT6
|
||||
#define BBAI_P8_04 DRA7XX_PIN_MMC3_DAT7
|
||||
#define BBAI_P8_05 DRA7XX_PIN_MMC3_DAT2
|
||||
#define BBAI_P8_06 DRA7XX_PIN_MMC3_DAT3
|
||||
#define BBAI_P8_07 DRA7XX_PIN_MCASP1_AXR14
|
||||
#define BBAI_P8_08 DRA7XX_PIN_MCASP1_AXR15
|
||||
#define BBAI_P8_09 DRA7XX_PIN_XREF_CLK1
|
||||
#define BBAI_P8_10 DRA7XX_PIN_MCASP1_AXR13
|
||||
#define BBAI_P8_11 DRA7XX_PIN_VIN1A_D7
|
||||
#define BBAI_P8_12 DRA7XX_PIN_VIN1A_D6
|
||||
#define BBAI_P8_13 DRA7XX_PIN_VIN2A_D10
|
||||
#define BBAI_P8_14 DRA7XX_PIN_VIN2A_D12
|
||||
|
||||
#define BBAI_P8_15A DRA7XX_PIN_VIN2A_D2
|
||||
#define BBAI_P8_15B DRA7XX_PIN_VIN2A_D19
|
||||
|
||||
#define BBAI_P8_16 DRA7XX_PIN_VIN2A_D21
|
||||
#define BBAI_P8_17 DRA7XX_PIN_VOUT1_D18
|
||||
#define BBAI_P8_18 DRA7XX_PIN_VIN2A_D8
|
||||
#define BBAI_P8_19 DRA7XX_PIN_VIN2A_D9
|
||||
#define BBAI_P8_20 DRA7XX_PIN_MMC3_CMD
|
||||
#define BBAI_P8_21 DRA7XX_PIN_MMC3_CLK
|
||||
#define BBAI_P8_22 DRA7XX_PIN_MMC3_DAT5
|
||||
#define BBAI_P8_23 DRA7XX_PIN_MMC3_DAT4
|
||||
#define BBAI_P8_24 DRA7XX_PIN_MMC3_DAT1
|
||||
#define BBAI_P8_25 DRA7XX_PIN_MMC3_DAT0
|
||||
#define BBAI_P8_26 DRA7XX_PIN_VIN2A_D20
|
||||
|
||||
#define BBAI_P8_27A DRA7XX_PIN_VOUT1_VSYNC
|
||||
#define BBAI_P8_27B DRA7XX_PIN_VOUT1_D19
|
||||
|
||||
#define BBAI_P8_28A DRA7XX_PIN_VOUT1_CLK
|
||||
#define BBAI_P8_28B DRA7XX_PIN_VOUT1_D20
|
||||
|
||||
#define BBAI_P8_29A DRA7XX_PIN_VOUT1_HSYNC
|
||||
#define BBAI_P8_29B DRA7XX_PIN_VOUT1_D21
|
||||
|
||||
#define BBAI_P8_30A DRA7XX_PIN_VOUT1_DE
|
||||
#define BBAI_P8_30B DRA7XX_PIN_VOUT1_D22
|
||||
|
||||
#define BBAI_P8_31A DRA7XX_PIN_VOUT1_D14
|
||||
#define BBAI_P8_31B DRA7XX_PIN_MCASP4_AXR0
|
||||
|
||||
#define BBAI_P8_32A DRA7XX_PIN_VOUT1_D15
|
||||
#define BBAI_P8_32B DRA7XX_PIN_MCASP4_AXR1
|
||||
|
||||
#define BBAI_P8_33A DRA7XX_PIN_VOUT1_D13
|
||||
#define BBAI_P8_33B DRA7XX_PIN_VIN1A_FLD0
|
||||
|
||||
#define BBAI_P8_34A DRA7XX_PIN_VOUT1_D11
|
||||
#define BBAI_P8_34B DRA7XX_PIN_VIN2A_VSYNC0
|
||||
|
||||
#define BBAI_P8_35A DRA7XX_PIN_VOUT1_D12
|
||||
#define BBAI_P8_35B DRA7XX_PIN_VIN1A_DE0
|
||||
|
||||
#define BBAI_P8_36A DRA7XX_PIN_VOUT1_D10
|
||||
#define BBAI_P8_36B DRA7XX_PIN_VIN2A_D0
|
||||
|
||||
#define BBAI_P8_37A DRA7XX_PIN_VOUT1_D8
|
||||
#define BBAI_P8_37B DRA7XX_PIN_MCASP4_FSX
|
||||
|
||||
#define BBAI_P8_38A DRA7XX_PIN_VOUT1_D9
|
||||
#define BBAI_P8_38B DRA7XX_PIN_MCASP4_ACLKX
|
||||
|
||||
#define BBAI_P8_39 DRA7XX_PIN_VOUT1_D6
|
||||
#define BBAI_P8_40 DRA7XX_PIN_VOUT1_D7
|
||||
#define BBAI_P8_41 DRA7XX_PIN_VOUT1_D4
|
||||
#define BBAI_P8_42 DRA7XX_PIN_VOUT1_D5
|
||||
#define BBAI_P8_43 DRA7XX_PIN_VOUT1_D2
|
||||
#define BBAI_P8_44 DRA7XX_PIN_VOUT1_D3
|
||||
|
||||
#define BBAI_P8_45A DRA7XX_PIN_VOUT1_D0
|
||||
#define BBAI_P8_45B DRA7XX_PIN_VOUT1_D16
|
||||
|
||||
#define BBAI_P8_46A DRA7XX_PIN_VOUT1_D1
|
||||
#define BBAI_P8_46B DRA7XX_PIN_VOUT1_D23
|
||||
|
||||
#define BBAI_P9_11A DRA7XX_PIN_MCASP3_AXR0
|
||||
#define BBAI_P9_11B DRA7XX_PIN_VOUT1_D17
|
||||
|
||||
#define BBAI_P9_12 DRA7XX_PIN_MCASP1_ACLKR
|
||||
|
||||
#define BBAI_P9_13A DRA7XX_PIN_MCASP3_AXR1
|
||||
#define BBAI_P9_13B DRA7XX_PIN_USB1_DRVVBUS
|
||||
|
||||
#define BBAI_P9_14 DRA7XX_PIN_VIN2A_D17
|
||||
#define BBAI_P9_15 DRA7XX_PIN_VIN1A_D8
|
||||
#define BBAI_P9_16 DRA7XX_PIN_VIN2A_D18
|
||||
|
||||
#define BBAI_P9_17A DRA7XX_PIN_SPI2_CS0
|
||||
#define BBAI_P9_17B DRA7XX_PIN_MCASP1_AXR1
|
||||
|
||||
#define BBAI_P9_18A DRA7XX_PIN_SPI2_D0
|
||||
#define BBAI_P9_18B DRA7XX_PIN_MCASP1_AXR0
|
||||
|
||||
#define BBAI_P9_19A DRA7XX_PIN_GPMC_A0
|
||||
#define BBAI_P9_19B DRA7XX_PIN_VIN2A_D5
|
||||
|
||||
#define BBAI_P9_20A DRA7XX_PIN_GPMC_A1
|
||||
#define BBAI_P9_20B DRA7XX_PIN_VIN2A_D4
|
||||
|
||||
#define BBAI_P9_21A DRA7XX_PIN_VIN1A_VSYNC0
|
||||
#define BBAI_P9_21B DRA7XX_PIN_SPI2_D1
|
||||
|
||||
#define BBAI_P9_22A DRA7XX_PIN_XREF_CLK2
|
||||
#define BBAI_P9_22B DRA7XX_PIN_SPI2_SCLK
|
||||
|
||||
#define BBAI_P9_23 DRA7XX_PIN_SPI1_CS1
|
||||
#define BBAI_P9_24 DRA7XX_PIN_GPIO6_15
|
||||
#define BBAI_P9_25 DRA7XX_PIN_XREF_CLK0
|
||||
|
||||
#define BBAI_P9_26A DRA7XX_PIN_GPIO6_14
|
||||
#define BBAI_P9_26B DRA7XX_PIN_VIN1A_D20
|
||||
|
||||
#define BBAI_P9_27A DRA7XX_PIN_VIN2A_D14
|
||||
#define BBAI_P9_27B DRA7XX_PIN_MCASP1_FSR
|
||||
|
||||
#define BBAI_P9_28 DRA7XX_PIN_MCASP1_AXR11
|
||||
|
||||
#define BBAI_P9_29A DRA7XX_PIN_MCASP1_AXR9
|
||||
#define BBAI_P9_29B DRA7XX_PIN_MCASP1_FSX
|
||||
|
||||
#define BBAI_P9_30 DRA7XX_PIN_MCASP1_AXR10
|
||||
|
||||
#define BBAI_P9_31A DRA7XX_PIN_MCASP1_AXR8
|
||||
#define BBAI_P9_31B DRA7XX_PIN_MCASP1_ACLKX
|
||||
|
||||
#define BBAI_P9_41A DRA7XX_PIN_XREF_CLK3
|
||||
#define BBAI_P9_41B DRA7XX_PIN_VIN2A_D6
|
||||
|
||||
#define BBAI_P9_42A DRA7XX_PIN_MCASP1_AXR12
|
||||
#define BBAI_P9_42B DRA7XX_PIN_VIN2A_D13
|
||||
|
||||
#endif
|
||||
|
||||
94
platforms/beaglebone/dt-bindings/pinctrl/omap.h
Executable file
94
platforms/beaglebone/dt-bindings/pinctrl/omap.h
Executable file
@ -0,0 +1,94 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* This header provides constants for OMAP pinctrl bindings.
|
||||
*
|
||||
* Copyright (C) 2009 Nokia
|
||||
* Copyright (C) 2009-2010 Texas Instruments
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_PINCTRL_OMAP_H
|
||||
#define _DT_BINDINGS_PINCTRL_OMAP_H
|
||||
|
||||
/* 34xx mux mode options for each pin. See TRM for options */
|
||||
#define MUX_MODE0 0
|
||||
#define MUX_MODE1 1
|
||||
#define MUX_MODE2 2
|
||||
#define MUX_MODE3 3
|
||||
#define MUX_MODE4 4
|
||||
#define MUX_MODE5 5
|
||||
#define MUX_MODE6 6
|
||||
#define MUX_MODE7 7
|
||||
|
||||
/* 24xx/34xx mux bit defines */
|
||||
#define PULL_ENA (1 << 3)
|
||||
#define PULL_UP (1 << 4)
|
||||
#define ALTELECTRICALSEL (1 << 5)
|
||||
|
||||
/* omap3/4/5 specific mux bit defines */
|
||||
#define INPUT_EN (1 << 8)
|
||||
#define OFF_EN (1 << 9)
|
||||
#define OFFOUT_EN (1 << 10)
|
||||
#define OFFOUT_VAL (1 << 11)
|
||||
#define OFF_PULL_EN (1 << 12)
|
||||
#define OFF_PULL_UP (1 << 13)
|
||||
#define WAKEUP_EN (1 << 14)
|
||||
#define WAKEUP_EVENT (1 << 15)
|
||||
|
||||
/* Active pin states */
|
||||
#define PIN_OUTPUT 0
|
||||
#define PIN_OUTPUT_PULLUP (PIN_OUTPUT | PULL_ENA | PULL_UP)
|
||||
#define PIN_OUTPUT_PULLDOWN (PIN_OUTPUT | PULL_ENA)
|
||||
#define PIN_INPUT INPUT_EN
|
||||
#define PIN_INPUT_PULLUP (PULL_ENA | INPUT_EN | PULL_UP)
|
||||
#define PIN_INPUT_PULLDOWN (PULL_ENA | INPUT_EN)
|
||||
|
||||
/* Off mode states */
|
||||
#define PIN_OFF_NONE 0
|
||||
#define PIN_OFF_OUTPUT_HIGH (OFF_EN | OFFOUT_EN | OFFOUT_VAL)
|
||||
#define PIN_OFF_OUTPUT_LOW (OFF_EN | OFFOUT_EN)
|
||||
#define PIN_OFF_INPUT_PULLUP (OFF_EN | OFFOUT_EN | OFF_PULL_EN | OFF_PULL_UP)
|
||||
#define PIN_OFF_INPUT_PULLDOWN (OFF_EN | OFFOUT_EN | OFF_PULL_EN)
|
||||
#define PIN_OFF_WAKEUPENABLE WAKEUP_EN
|
||||
|
||||
/*
|
||||
* Macros to allow using the absolute physical address instead of the
|
||||
* padconf registers instead of the offset from padconf base.
|
||||
*/
|
||||
#define OMAP_IOPAD_OFFSET(pa, offset) (((pa) & 0xffff) - (offset))
|
||||
|
||||
#define OMAP2420_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0030) (val)
|
||||
#define OMAP2430_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2030) (val)
|
||||
#define OMAP3_CORE1_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2030) (val)
|
||||
#define OMAP3430_CORE2_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x25d8) (val)
|
||||
#define OMAP3630_CORE2_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x25a0) (val)
|
||||
#define OMAP3_WKUP_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2a00) (val)
|
||||
#define DM814X_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val)
|
||||
#define DM816X_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val)
|
||||
#define AM33XX_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val)
|
||||
#define AM33XX_PADCONF(pa, dir, mux) OMAP_IOPAD_OFFSET((pa), 0x0800) ((dir) | (mux))
|
||||
#define AM4372_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val)
|
||||
#define DRA7XX_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x3400) (val)
|
||||
|
||||
/*
|
||||
* Macros to allow using the offset from the padconf physical address
|
||||
* instead of the offset from padconf base.
|
||||
*/
|
||||
#define OMAP_PADCONF_OFFSET(offset, base_offset) ((offset) - (base_offset))
|
||||
|
||||
#define OMAP4_IOPAD(offset, val) OMAP_PADCONF_OFFSET((offset), 0x0040) (val)
|
||||
#define OMAP5_IOPAD(offset, val) OMAP_PADCONF_OFFSET((offset), 0x0040) (val)
|
||||
|
||||
/*
|
||||
* Define some commonly used pins configured by the boards.
|
||||
* Note that some boards use alternative pins, so check
|
||||
* the schematics before using these.
|
||||
*/
|
||||
#define OMAP3_UART1_RX 0x152
|
||||
#define OMAP3_UART2_RX 0x14a
|
||||
#define OMAP3_UART3_RX 0x16e
|
||||
#define OMAP4_UART2_RX 0xdc
|
||||
#define OMAP4_UART3_RX 0x104
|
||||
#define OMAP4_UART4_RX 0x11c
|
||||
|
||||
#endif
|
||||
|
||||
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5
platforms/beaglebone/uEnv.txt
Normal file
5
platforms/beaglebone/uEnv.txt
Normal file
@ -0,0 +1,5 @@
|
||||
uname_r=4.14.71-ti-r80
|
||||
enable_uboot_overlays=1
|
||||
uboot_overlay_pru=/lib/firmware/AM335X-PRU-RPROC-4-14-TI-00A0.dtbo
|
||||
dtb_overlay=/lib/firmware/VE-2IN-LCD.dtbo
|
||||
cmdline=coherent_pool=1M net.ifnames=0 quiet
|
||||
Loading…
x
Reference in New Issue
Block a user