mirror of
https://github.com/YikeStone/MT7601u.git
synced 2025-08-03 03:14:08 +05:30
437 lines
8.4 KiB
C
437 lines
8.4 KiB
C
/*
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*/
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#include "rt_config.h"
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#ifdef RLT_MAC
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#ifndef MT7601
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NDIS_STATUS NICInitBBP(RTMP_ADAPTER *pAd)
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{
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INT idx;
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/* Read BBP register, make sure BBP is up and running before write new data*/
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if (rlt_bbp_is_ready(pAd) == FALSE)
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return NDIS_STATUS_FAILURE;
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/* re-config specific BBP registers for individual chip */
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if (pAd->chipCap.pBBPRegTable)
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{
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RTMP_REG_PAIR *reg = (RTMP_REG_PAIR *)pAd->chipCap.pBBPRegTable;
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for (idx = 0; idx < pAd->chipCap.bbpRegTbSize; idx++)
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{
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RTMP_BBP_IO_WRITE32(pAd, reg[idx].Register, reg[idx].Value);
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DBGPRINT(RT_DEBUG_TRACE, ("BBP[%x]=0x%x\n",
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reg[idx].Register, reg[idx].Value));
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}
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}
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if (pAd->chipOps.AsicBbpInit != NULL)
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pAd->chipOps.AsicBbpInit(pAd);
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// TODO: shiang-6590, check these bbp registers if need to remap to new BBP_Registers
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return NDIS_STATUS_SUCCESS;
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}
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INT rtmp_bbp_set_txdac(struct _RTMP_ADAPTER *pAd, INT tx_dac)
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{
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UINT32 txbe, txbe_r5 = 0;
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RTMP_BBP_IO_READ32(pAd, TXBE_R5, &txbe_r5);
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txbe = txbe_r5 & (~0x3);
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switch (tx_dac)
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{
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case 2:
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txbe |= 0x3;
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break;
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case 1:
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case 0:
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default:
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txbe &= (~0x3);
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break;
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}
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if (txbe != txbe_r5)
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RTMP_BBP_IO_WRITE32(pAd, TXBE_R5, txbe);
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return TRUE;
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}
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INT rtmp_bbp_set_rxpath(struct _RTMP_ADAPTER *pAd, INT rxpath)
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{
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UINT32 agc, agc_r0 = 0;
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RTMP_BBP_IO_READ32(pAd, AGC1_R0, &agc_r0);
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agc = agc_r0 & (~0x18);
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if(rxpath == 2)
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agc |= (0x8);
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else if(rxpath == 1)
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agc |= (0x0);
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if (agc != agc_r0)
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RTMP_BBP_IO_WRITE32(pAd, AGC1_R0, agc);
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//DBGPRINT(RT_DEBUG_OFF, ("%s(): rxpath=%d, Set AGC1_R0=0x%x, agc_r0=0x%x\n", __FUNCTION__, rxpath, agc, agc_r0));
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// RTMP_BBP_IO_READ32(pAd, AGC1_R0, &agc);
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//DBGPRINT(RT_DEBUG_OFF, ("%s(): rxpath=%d, After write, Get AGC1_R0=0x%x,\n", __FUNCTION__, rxpath, agc));
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return TRUE;
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}
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static UCHAR vht_prim_ch_val[] = {
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42, 36, 0,
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42, 40, 1,
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42, 44, 2,
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42, 48, 3,
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58, 52, 0,
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58, 56, 1,
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58, 60, 2,
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58, 64, 3,
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106, 100, 0,
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106, 104, 1,
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106, 108, 2,
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106, 112, 3,
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122, 116, 0,
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122, 120, 1,
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122, 124, 2,
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122, 128, 3,
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138, 132, 0,
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138, 136, 1,
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138, 140, 2,
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138, 144, 3,
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155, 149, 0,
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155, 153, 1,
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155, 157, 2,
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155, 161, 3
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};
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INT rtmp_bbp_set_ctrlch(struct _RTMP_ADAPTER *pAd, INT ext_ch)
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{
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UINT32 agc, agc_r0 = 0;
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UINT32 be, be_r0 = 0;
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RTMP_BBP_IO_READ32(pAd, AGC1_R0, &agc_r0);
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agc = agc_r0 & (~0x300);
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RTMP_BBP_IO_READ32(pAd, TXBE_R0, &be_r0);
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be = (be_r0 & (~0x03));
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#ifdef DOT11_VHT_AC
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if (pAd->CommonCfg.BBPCurrentBW == BW_80 &&
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pAd->CommonCfg.Channel >= 36 &&
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pAd->CommonCfg.vht_cent_ch)
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{
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if (pAd->CommonCfg.Channel < pAd->CommonCfg.vht_cent_ch)
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{
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switch (pAd->CommonCfg.vht_cent_ch - pAd->CommonCfg.Channel)
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{
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case 6:
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be |= 0;
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agc |=0x000;
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break;
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case 2:
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be |= 1;
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agc |=0x100;
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break;
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}
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}
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else if (pAd->CommonCfg.Channel > pAd->CommonCfg.vht_cent_ch)
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{
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switch (pAd->CommonCfg.Channel - pAd->CommonCfg.vht_cent_ch)
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{
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case 6:
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be |= 0x3;
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agc |=0x300;
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break;
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case 2:
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be |= 0x2;
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agc |=0x200;
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break;
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}
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}
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}
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else
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#endif /* DOT11_VHT_AC */
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{
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switch (ext_ch)
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{
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case EXTCHA_BELOW:
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agc |= 0x100;
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be |= 0x01;
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break;
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case EXTCHA_ABOVE:
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agc &= (~0x300);
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be &= (~0x03);
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break;
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case EXTCHA_NONE:
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default:
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agc &= (~0x300);
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be &= (~0x03);
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break;
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}
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}
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if (agc != agc_r0)
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RTMP_BBP_IO_WRITE32(pAd, AGC1_R0, agc);
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if (be != be_r0)
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RTMP_BBP_IO_WRITE32(pAd, TXBE_R0, be);
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//DBGPRINT(RT_DEBUG_OFF, ("%s(): ext_ch=%d, Set AGC1_R0=0x%x, agc_r0=0x%x\n", __FUNCTION__, ext_ch, agc, agc_r0));
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// RTMP_BBP_IO_READ32(pAd, AGC1_R0, &agc);
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//DBGPRINT(RT_DEBUG_OFF, ("%s(): ext_ch=%d, After write, Get AGC1_R0=0x%x,\n", __FUNCTION__, ext_ch, agc));
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return TRUE;
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}
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/*
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<<Gamma2.1 Control Registers Rev1.3.pdf>>
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BBP bandwidth (CORE_R1[4:3]) change procedure:
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1. Hold BBP in reset by setting CORE_R4[0] to '1'
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2. Wait 0.5 us to ensure BBP is in the idle State
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3. Change BBP bandwidth with CORE_R1[4:3]
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CORE_R1 (Bit4:3)
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0: 20MHz
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1: 10MHz (11J)
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2: 40MHz
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3: 80MHz
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4. Wait 0.5 us for BBP clocks to settle
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5. Release BBP from reset by clearing CORE_R4[0]
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*/
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INT rtmp_bbp_set_bw(struct _RTMP_ADAPTER *pAd, INT bw)
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{
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UINT32 core, core_r1 = 0, core_r4 = 0;
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UINT32 agc, agc_r0 = 0;
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RTMP_BBP_IO_READ32(pAd, CORE_R1, &core_r1);
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core = (core_r1 & (~0x18));
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RTMP_BBP_IO_READ32(pAd, AGC1_R0, &agc_r0);
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agc = agc_r0 & (~0x7000);
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switch (bw)
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{
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case BW_80:
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core |= 0x18;
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agc |= 0x7000;
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break;
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case BW_40:
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core |= 0x10;
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agc |= 0x3000;
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break;
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case BW_20:
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core &= (~0x18);
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agc |= 0x1000;
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break;
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case BW_10:
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core |= 0x08;
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agc |= 0x1000;
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break;
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}
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if (core != core_r1)
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{
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#ifdef RT65xx
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if (IS_RT6590(pAd))
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{
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/*
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Hold BBP in reset by setting CORE_R4[0]=1
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*/
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RTMP_BBP_IO_READ32(pAd, CORE_R4, &core_r4);
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core_r4 |= 0x00000001;
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RTMP_BBP_IO_WRITE32(pAd, CORE_R4, core_r4);
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/*
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Wait 0.5 us to ensure BBP is in the idle state.
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*/
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RtmpOsUsDelay(1);
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}
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#endif /* RT65xx */
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RTMP_BBP_IO_WRITE32(pAd, CORE_R1, core);
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#ifdef RT65xx
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if (IS_RT6590(pAd))
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{
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/*
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Wait 0.5 us for BBP clocks to settle.
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*/
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RtmpOsUsDelay(1);
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/*
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Release BBP from reset by clearing CORE_R4[0].
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*/
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RTMP_BBP_IO_READ32(pAd, CORE_R4, &core_r4);
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core_r4 &= ~(0x00000001);
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RTMP_BBP_IO_WRITE32(pAd, CORE_R4, core_r4);
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}
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#endif /* RT65xx */
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}
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if (agc != agc_r0) {
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RTMP_BBP_IO_WRITE32(pAd, AGC1_R0, agc);
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//DBGPRINT(RT_DEBUG_OFF, ("%s(): bw=%d, Set AGC1_R0=0x%x, agc_r0=0x%x\n", __FUNCTION__, bw, agc, agc_r0));
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// RTMP_BBP_IO_READ32(pAd, AGC1_R0, &agc);
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//DBGPRINT(RT_DEBUG_OFF, ("%s(): bw=%d, After write, Get AGC1_R0=0x%x,\n", __FUNCTION__, bw, agc));
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}
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pAd->CommonCfg.BBPCurrentBW = bw;
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return TRUE;
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}
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INT rtmp_bbp_set_mmps(struct _RTMP_ADAPTER *pAd, BOOLEAN ReduceCorePower)
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{
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UINT32 bbp_val, org_val;
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RTMP_BBP_IO_READ32(pAd, AGC1_R0, &org_val);
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bbp_val = org_val;
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if (ReduceCorePower)
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bbp_val |= 0x04;
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else
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bbp_val &= ~0x04;
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if (bbp_val != org_val)
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RTMP_BBP_IO_WRITE32(pAd, AGC1_R0, bbp_val);
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return TRUE;
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}
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INT rtmp_bbp_get_agc(struct _RTMP_ADAPTER *pAd, CHAR *agc, RX_CHAIN_IDX chain)
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{
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UCHAR idx, val;
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UINT32 bbp_val, bbp_reg = AGC1_R8;
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if (((pAd->MACVersion & 0xffff0000) < 0x28830000) ||
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(pAd->Antenna.field.RxPath == 1))
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{
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chain = RX_CHAIN_0;
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}
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idx = val = 0;
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while(chain != 0)
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{
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if (idx >= pAd->Antenna.field.RxPath)
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break;
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if (chain & 0x01)
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{
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RTMP_BBP_IO_READ32(pAd, bbp_reg, &bbp_val);
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val = ((bbp_val & (0x0000ff00)) >> 8) & 0xff;
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break;
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}
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chain >>= 1;
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bbp_reg += 4;
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idx++;
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}
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*agc = val;
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return NDIS_STATUS_SUCCESS;
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}
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INT rtmp_bbp_set_agc(struct _RTMP_ADAPTER *pAd, UCHAR agc, RX_CHAIN_IDX chain)
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{
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UCHAR idx = 0;
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UINT32 bbp_val, bbp_reg = AGC1_R8;
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if (((pAd->MACVersion & 0xf0000000) < 0x28830000) ||
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(pAd->Antenna.field.RxPath == 1))
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{
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chain = RX_CHAIN_0;
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}
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while (chain != 0)
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{
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if (idx >= pAd->Antenna.field.RxPath)
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break;
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if (idx & 0x01)
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{
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RTMP_BBP_IO_READ32(pAd, bbp_reg, &bbp_val);
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bbp_val = (bbp_val & 0xffff00ff) | (agc << 8);
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RTMP_BBP_IO_WRITE32(pAd, bbp_reg, bbp_val);
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DBGPRINT(RT_DEBUG_INFO,
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("%s(Idx):Write(R%d,val:0x%x) to Chain(0x%x, idx:%d)\n",
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__FUNCTION__, bbp_reg, bbp_val, chain, idx));
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}
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chain >>= 1;
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bbp_reg += 4;
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idx++;
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}
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return TRUE;
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}
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INT rtmp_bbp_set_filter_coefficient_ctrl(RTMP_ADAPTER *pAd, UCHAR Channel)
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{
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UINT32 bbp_val = 0, org_val = 0;
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if (Channel == 14)
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{
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/* when Channel==14 && Mode==CCK && BandWidth==20M, BBP R4 bit5=1 */
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RTMP_BBP_IO_READ32(pAd, CORE_R1, &org_val);
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bbp_val = org_val;
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if (WMODE_EQUAL(pAd->CommonCfg.PhyMode, WMODE_B))
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bbp_val |= 0x20;
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else
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bbp_val &= (~0x20);
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if (bbp_val != org_val)
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RTMP_BBP_IO_WRITE32(pAd, CORE_R1, bbp_val);
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}
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return TRUE;
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}
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UCHAR rtmp_bbp_get_random_seed(RTMP_ADAPTER *pAd)
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{
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UINT32 value, value2;
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UCHAR seed;
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RTMP_BBP_IO_READ32(pAd, AGC1_R16, &value);
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seed = (UCHAR)((value & 0xff) ^ ((value & 0xff00) >> 8)^
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((value & 0xff0000) >> 16));
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RTMP_BBP_IO_READ32(pAd, RXO_R9, &value2);
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return (UCHAR)(seed ^ (value2 & 0xff)^ ((value2 & 0xff00) >> 8));
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}
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INT rlt_bbp_is_ready(struct _RTMP_ADAPTER *pAd)
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{
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INT idx = 0;
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UINT32 val;
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do
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{
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RTMP_BBP_IO_READ32(pAd, CORE_R0, &val);
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if (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST))
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return FALSE;
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DBGPRINT(RT_DEBUG_TRACE, ("BBP version = %x\n", val));
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} while ((++idx < 20) && ((val == 0xffffffff) || (val == 0x0)));
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return (((val == 0xffffffff) || (val == 0x0)) ? FALSE : TRUE);
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}
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#endif /* MT7601 */
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#endif /* RLT_MAC */
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