mirror of
https://github.com/YikeStone/MT7601u.git
synced 2025-08-03 03:14:08 +05:30
269 lines
14 KiB
C
269 lines
14 KiB
C
/****************************************************************************
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* Ralink Tech Inc.
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* 4F, No. 2 Technology 5th Rd.
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* Science-based Industrial Park
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* Hsin-chu, Taiwan, R.O.C.
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* (c) Copyright 2002, Ralink Technology, Inc.
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*
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* All rights reserved. Ralink's source code is an unpublished work and the
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* use of a copyright notice does not imply otherwise. This source code
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* contains confidential trade secret material of Ralink Tech. Any attemp
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* or participation in deciphering, decoding, reverse engineering or in any
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* way altering the source code is stricitly prohibited, unless the prior
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* written consent of Ralink Technology, Inc. is obtained.
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****************************************************************************
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Module Name:
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rt6590.h
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Abstract:
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Revision History:
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Who When What
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--------- ---------- ----------------------------------------------
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*/
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#ifndef __MT7601_H__
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#define __MT7601_H__
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struct _RTMP_ADAPTER;
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#define MAC_VERSION ""
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#define BBP_VERSION "MT7601E2_BBP_CSD_20121019"
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#define RF_VERSION "RT6390_RF_Register_20121122"
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#define NIC6590_PCIe_DEVICE_ID 0x6590
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#define MAX_RF_ID 127
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#define MAC_RF_BANK 7
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#define MAX_CHECK_COUNT 200
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#define MT7601_VALID_EEPROM_VERSION 0x0C
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#define ENABLE_WLAN_FUN(__WlanFunCtrl)\
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{\
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__WlanFunCtrl.field.WLAN_CLK_EN = 1;\
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__WlanFunCtrl.field.WLAN_EN = 1;\
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}
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#define DISABLE_WLAN_FUN(__WlanFunCtrl)\
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{\
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__WlanFunCtrl.field.PCIE_APP0_CLK_REQ = 0;\
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__WlanFunCtrl.field.WLAN_EN = 0;\
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__WlanFunCtrl.field.WLAN_CLK_EN = 0;\
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}
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#define MT7601_WSC_HDR_BTN_GPIO 0x400
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#define MT7601_WSC_HDR_BTN_MR_PRESS_FLG_GET(__pAd, __FlgIsPressed) \
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{ \
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UINT32 __gpio_value; \
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RTMP_IO_READ32(__pAd, WLAN_FUN_CTRL, (&__gpio_value)); \
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if (__gpio_value & MT7601_WSC_HDR_BTN_GPIO) \
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__FlgIsPressed = 0; \
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else \
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__FlgIsPressed = 1; \
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}
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#define RF_PA_MODE0_DECODE 0
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#define RF_PA_MODE1_DECODE 8847 // 1.08 * 8192
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#define RF_PA_MODE2_DECODE -5734 // -0.7 * 8192
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#define RF_PA_MODE3_DECODE -5734 // -0.7 * 8192
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#define MT7601_E2_TEMPERATURE_SLOPE 39
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#define BW20_MCS_POWER_CCK_1M ((pAd->Tx20MPwrCfgGBand[0] & 0xFF) < 0x20)?(pAd->Tx20MPwrCfgGBand[0] & 0xFF):(CHAR)((pAd->Tx20MPwrCfgGBand[0] & 0xFF) - 0x40)
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#define BW20_MCS_POWER_CCK_2M ((pAd->Tx20MPwrCfgGBand[0] & 0xFF) < 0x20)?(pAd->Tx20MPwrCfgGBand[0] & 0xFF):(CHAR)((pAd->Tx20MPwrCfgGBand[0] & 0xFF) - 0x40)
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#define BW20_MCS_POWER_CCK_5M (((pAd->Tx20MPwrCfgGBand[0] & 0xFF00) >> 8) < 0x20)?((pAd->Tx20MPwrCfgGBand[0] & 0xFF00) >> 8):(CHAR)(((pAd->Tx20MPwrCfgGBand[0] & 0xFF00) >> 8)-0x40)
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#define BW20_MCS_POWER_CCK_11M (((pAd->Tx20MPwrCfgGBand[0] & 0xFF00) >> 8) < 0x20)?((pAd->Tx20MPwrCfgGBand[0] & 0xFF00) >> 8):(CHAR)(((pAd->Tx20MPwrCfgGBand[0] & 0xFF00) >> 8)-0x40)
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#define BW40_MCS_POWER_CCK_1M ((pAd->Tx40MPwrCfgGBand[0] & 0xFF) < 0x20)?(pAd->Tx40MPwrCfgGBand[0] & 0xFF) :(CHAR)(((pAd->Tx40MPwrCfgGBand[0] & 0xFF) < 0x20)-0x40)
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#define BW40_MCS_POWER_CCK_2M ((pAd->Tx40MPwrCfgGBand[0] & 0xFF) < 0x20)?(pAd->Tx40MPwrCfgGBand[0] & 0xFF) :(CHAR)(((pAd->Tx40MPwrCfgGBand[0] & 0xFF) < 0x20)-0x40)
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#define BW40_MCS_POWER_CCK_5M (((pAd->Tx40MPwrCfgGBand[0] & 0xFF00) >> 8) < 0x20)?((pAd->Tx40MPwrCfgGBand[0] & 0xFF00) >> 8):(CHAR)(((pAd->Tx40MPwrCfgGBand[0] & 0xFF00) >> 8)-0x40)
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#define BW40_MCS_POWER_CCK_11M (((pAd->Tx40MPwrCfgGBand[0] & 0xFF00) >> 8) < 0x20)?((pAd->Tx40MPwrCfgGBand[0] & 0xFF00) >> 8):(CHAR)(((pAd->Tx40MPwrCfgGBand[0] & 0xFF00) >> 8)-0x40)
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#define BW20_MCS_POWER_OFDM_6M (((pAd->Tx20MPwrCfgGBand[0] & 0xFF0000) >> 16) < 0x20)?((pAd->Tx20MPwrCfgGBand[0] & 0xFF0000) >> 16):(CHAR)(((pAd->Tx20MPwrCfgGBand[0] & 0xFF0000) >> 16)-0x40)
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#define BW20_MCS_POWER_OFDM_9M (((pAd->Tx20MPwrCfgGBand[0] & 0xFF0000) >> 16) < 0x20)?((pAd->Tx20MPwrCfgGBand[0] & 0xFF0000) >> 16):(CHAR)(((pAd->Tx20MPwrCfgGBand[0] & 0xFF0000) >> 16)-0x40)
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#define BW20_MCS_POWER_OFDM_12M (((pAd->Tx20MPwrCfgGBand[0] & 0xFF000000) >> 24) < 0x20)?((pAd->Tx20MPwrCfgGBand[0] & 0xFF000000) >> 24):(CHAR)(((pAd->Tx20MPwrCfgGBand[0] & 0xFF000000) >> 24)-0x40)
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#define BW20_MCS_POWER_OFDM_18M (((pAd->Tx20MPwrCfgGBand[0] & 0xFF000000) >> 24) < 0x20)?((pAd->Tx20MPwrCfgGBand[0] & 0xFF000000) >> 24):(CHAR)(((pAd->Tx20MPwrCfgGBand[0] & 0xFF000000) >> 24)-0x40)
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#define BW20_MCS_POWER_OFDM_24M ((pAd->Tx20MPwrCfgGBand[1] & 0xFF) < 0x20)?(pAd->Tx20MPwrCfgGBand[1] & 0xFF):(CHAR)((pAd->Tx20MPwrCfgGBand[1] & 0xFF)-0x40)
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#define BW20_MCS_POWER_OFDM_36M ((pAd->Tx20MPwrCfgGBand[1] & 0xFF) < 0x20)?(pAd->Tx20MPwrCfgGBand[1] & 0xFF):(CHAR)((pAd->Tx20MPwrCfgGBand[1] & 0xFF)-0x40)
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#define BW20_MCS_POWER_OFDM_48M (((pAd->Tx20MPwrCfgGBand[1] & 0xFF00) >> 8) < 0x20)?((pAd->Tx20MPwrCfgGBand[1] & 0xFF00) >> 8):(CHAR)(((pAd->Tx20MPwrCfgGBand[1] & 0xFF00) >> 8)-0x40)
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#define BW20_MCS_POWER_OFDM_54M (((pAd->Tx20MPwrCfgGBand[1] & 0xFF00) >> 8) < 0x20)?((pAd->Tx20MPwrCfgGBand[1] & 0xFF00) >> 8):(CHAR)(((pAd->Tx20MPwrCfgGBand[1] & 0xFF00) >> 8)-0x40)
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#define BW40_MCS_POWER_OFDM_6M (((pAd->Tx40MPwrCfgGBand[0] & 0xFF0000) >> 16) < 0x20)?((pAd->Tx40MPwrCfgGBand[0] & 0xFF0000) >> 16):(CHAR)(((pAd->Tx40MPwrCfgGBand[0] & 0xFF0000) >> 16)-0x40)
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#define BW40_MCS_POWER_OFDM_9M (((pAd->Tx40MPwrCfgGBand[0] & 0xFF0000) >> 16) < 0x20)?((pAd->Tx40MPwrCfgGBand[0] & 0xFF0000) >> 16):(CHAR)(((pAd->Tx40MPwrCfgGBand[0] & 0xFF0000) >> 16)-0x40)
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#define BW40_MCS_POWER_OFDM_12M (((pAd->Tx40MPwrCfgGBand[0] & 0xFF000000) >> 24) < 0x20)?((pAd->Tx40MPwrCfgGBand[0] & 0xFF000000) >> 24):(CHAR)(((pAd->Tx40MPwrCfgGBand[0] & 0xFF000000) >> 24)-0x40)
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#define BW40_MCS_POWER_OFDM_18M (((pAd->Tx40MPwrCfgGBand[0] & 0xFF000000) >> 24) < 0x20)?((pAd->Tx40MPwrCfgGBand[0] & 0xFF000000) >> 24):(CHAR)(((pAd->Tx40MPwrCfgGBand[0] & 0xFF000000) >> 24)-0x40)
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#define BW40_MCS_POWER_OFDM_24M ((pAd->Tx40MPwrCfgGBand[1] & 0xFF) < 0x20)?(pAd->Tx40MPwrCfgGBand[1] & 0xFF):(CHAR)((pAd->Tx40MPwrCfgGBand[1] & 0xFF)-0x40)
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#define BW40_MCS_POWER_OFDM_36M ((pAd->Tx40MPwrCfgGBand[1] & 0xFF) < 0x20)?(pAd->Tx40MPwrCfgGBand[1] & 0xFF):(CHAR)((pAd->Tx40MPwrCfgGBand[1] & 0xFF)-0x40)
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#define BW40_MCS_POWER_OFDM_48M (((pAd->Tx40MPwrCfgGBand[1] & 0xFF00) >> 8) < 0x20)?((pAd->Tx40MPwrCfgGBand[1] & 0xFF00) >> 8):(CHAR)(((pAd->Tx40MPwrCfgGBand[1] & 0xFF00) >> 8)-0x40)
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#define BW40_MCS_POWER_OFDM_54M (((pAd->Tx40MPwrCfgGBand[1] & 0xFF00) >> 8) < 0x20)?((pAd->Tx40MPwrCfgGBand[1] & 0xFF00) >> 8):(CHAR)(((pAd->Tx40MPwrCfgGBand[1] & 0xFF00) >> 8)-0x40)
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#define BW20_MCS_POWER_HT_MCS0 (((pAd->Tx20MPwrCfgGBand[1] & 0xFF0000) >> 16) < 0x20)?((pAd->Tx20MPwrCfgGBand[1] & 0xFF0000) >> 16):(CHAR)(((pAd->Tx20MPwrCfgGBand[1] & 0xFF0000) >> 16)-0x40)
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#define BW20_MCS_POWER_HT_MCS1 (((pAd->Tx20MPwrCfgGBand[1] & 0xFF0000) >> 16) < 0x20)?((pAd->Tx20MPwrCfgGBand[1] & 0xFF0000) >> 16):(CHAR)(((pAd->Tx20MPwrCfgGBand[1] & 0xFF0000) >> 16)-0x40)
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#define BW20_MCS_POWER_HT_MCS2 (((pAd->Tx20MPwrCfgGBand[1] & 0xFF000000) >> 24) < 0x20)?((pAd->Tx20MPwrCfgGBand[1] & 0xFF000000) >> 24):(CHAR)(((pAd->Tx20MPwrCfgGBand[1] & 0xFF000000) >> 24)-0x40)
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#define BW20_MCS_POWER_HT_MCS3 (((pAd->Tx20MPwrCfgGBand[1] & 0xFF000000) >> 24) < 0x20)?((pAd->Tx20MPwrCfgGBand[1] & 0xFF000000) >> 24):(CHAR)(((pAd->Tx20MPwrCfgGBand[1] & 0xFF000000) >> 24)-0x40)
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#define BW20_MCS_POWER_HT_MCS4 ((pAd->Tx20MPwrCfgGBand[2] & 0xFF) < 0x20)?(pAd->Tx20MPwrCfgGBand[2] & 0xFF):(CHAR)((pAd->Tx20MPwrCfgGBand[2] & 0xFF)-0x40)
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#define BW20_MCS_POWER_HT_MCS5 ((pAd->Tx20MPwrCfgGBand[2] & 0xFF) < 0x20)?(pAd->Tx20MPwrCfgGBand[2] & 0xFF):(CHAR)((pAd->Tx20MPwrCfgGBand[2] & 0xFF)-0x40)
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#define BW20_MCS_POWER_HT_MCS6 (((pAd->Tx20MPwrCfgGBand[2] & 0xFF00 ) >> 8) < 0x20)?((pAd->Tx20MPwrCfgGBand[2] & 0xFF00 ) >> 8):(CHAR)(((pAd->Tx20MPwrCfgGBand[2] & 0xFF00 ) >> 8)-0x40)
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#define BW20_MCS_POWER_HT_MCS7 (((pAd->Tx20MPwrCfgGBand[2] & 0xFF00 ) >> 8) < 0x20)?((pAd->Tx20MPwrCfgGBand[2] & 0xFF00 ) >> 8):(CHAR)(((pAd->Tx20MPwrCfgGBand[2] & 0xFF00 ) >> 8)-0x40)
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#define BW40_MCS_POWER_HT_MCS0 (((pAd->Tx40MPwrCfgGBand[1] & 0xFF0000) >> 16) < 0x20)?((pAd->Tx40MPwrCfgGBand[1] & 0xFF0000) >> 16):(CHAR)(((pAd->Tx40MPwrCfgGBand[1] & 0xFF0000) >> 16)-0x40)
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#define BW40_MCS_POWER_HT_MCS1 (((pAd->Tx40MPwrCfgGBand[1] & 0xFF0000) >> 16) < 0x20)?((pAd->Tx40MPwrCfgGBand[1] & 0xFF0000) >> 16):(CHAR)(((pAd->Tx40MPwrCfgGBand[1] & 0xFF0000) >> 16)-0x40)
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#define BW40_MCS_POWER_HT_MCS2 (((pAd->Tx40MPwrCfgGBand[1] & 0xFF000000) >> 24) < 0x20)?((pAd->Tx40MPwrCfgGBand[1] & 0xFF000000) >> 24):(CHAR)(((pAd->Tx40MPwrCfgGBand[1] & 0xFF000000) >> 24)-0x40)
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#define BW40_MCS_POWER_HT_MCS3 (((pAd->Tx40MPwrCfgGBand[1] & 0xFF000000) >> 24) < 0x20)?((pAd->Tx40MPwrCfgGBand[1] & 0xFF000000) >> 24):(CHAR)(((pAd->Tx40MPwrCfgGBand[1] & 0xFF000000) >> 24)-0x40)
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#define BW40_MCS_POWER_HT_MCS4 ((pAd->Tx40MPwrCfgGBand[2] & 0xFF) < 0x20)?(pAd->Tx40MPwrCfgGBand[2] & 0xFF):(CHAR)((pAd->Tx40MPwrCfgGBand[2] & 0xFF)-0x40)
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#define BW40_MCS_POWER_HT_MCS5 ((pAd->Tx40MPwrCfgGBand[2] & 0xFF) < 0x20)?(pAd->Tx40MPwrCfgGBand[2] & 0xFF):(CHAR)((pAd->Tx40MPwrCfgGBand[2] & 0xFF)-0x40)
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#define BW40_MCS_POWER_HT_MCS6 (((pAd->Tx40MPwrCfgGBand[2] & 0xFF00) >> 8) < 0x20)?((pAd->Tx40MPwrCfgGBand[2] & 0xFF00) >> 8):(CHAR)(((pAd->Tx40MPwrCfgGBand[2] & 0xFF00) >> 8)-0x40)
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#define BW40_MCS_POWER_HT_MCS7 (((pAd->Tx40MPwrCfgGBand[2] & 0xFF00) >> 8) < 0x20)?((pAd->Tx40MPwrCfgGBand[2] & 0xFF00) >> 8):(CHAR)(((pAd->Tx40MPwrCfgGBand[2] & 0xFF00) >> 8)-0x40)
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#define RF_PA_MODE_CCK_1M (pAd->chipCap.PAModeCCK[0])
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#define RF_PA_MODE_CCK_2M (pAd->chipCap.PAModeCCK[1])
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#define RF_PA_MODE_CCK_5M (pAd->chipCap.PAModeCCK[2])
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#define RF_PA_MODE_CCK_11M (pAd->chipCap.PAModeCCK[3])
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#define RF_PA_MODE_OFDM_6M (pAd->chipCap.PAModeOFDM[0])
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#define RF_PA_MODE_OFDM_9M (pAd->chipCap.PAModeOFDM[1])
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#define RF_PA_MODE_OFDM_12M (pAd->chipCap.PAModeOFDM[2])
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#define RF_PA_MODE_OFDM_18M (pAd->chipCap.PAModeOFDM[3])
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#define RF_PA_MODE_OFDM_24M (pAd->chipCap.PAModeOFDM[4])
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#define RF_PA_MODE_OFDM_36M (pAd->chipCap.PAModeOFDM[5])
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#define RF_PA_MODE_OFDM_48M (pAd->chipCap.PAModeOFDM[6])
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#define RF_PA_MODE_OFDM_54M (pAd->chipCap.PAModeOFDM[7])
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#define RF_PA_MODE_HT_MCS0 (pAd->chipCap.PAModeHT[0])
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#define RF_PA_MODE_HT_MCS1 (pAd->chipCap.PAModeHT[1])
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#define RF_PA_MODE_HT_MCS2 (pAd->chipCap.PAModeHT[2])
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#define RF_PA_MODE_HT_MCS3 (pAd->chipCap.PAModeHT[3])
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#define RF_PA_MODE_HT_MCS4 (pAd->chipCap.PAModeHT[4])
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#define RF_PA_MODE_HT_MCS5 (pAd->chipCap.PAModeHT[5])
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#define RF_PA_MODE_HT_MCS6 (pAd->chipCap.PAModeHT[6])
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#define RF_PA_MODE_HT_MCS7 (pAd->chipCap.PAModeHT[7])
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#define RF_PA_MODE_HT_MCS8 (pAd->chipCap.PAModeHT[8])
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#define RF_PA_MODE_HT_MCS9 (pAd->chipCap.PAModeHT[9])
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#define RF_PA_MODE_HT_MCS10 (pAd->chipCap.PAModeHT[10])
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#define RF_PA_MODE_HT_MCS11 (pAd->chipCap.PAModeHT[11])
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#define RF_PA_MODE_HT_MCS12 (pAd->chipCap.PAModeHT[12])
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#define RF_PA_MODE_HT_MCS13 (pAd->chipCap.PAModeHT[13])
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#define RF_PA_MODE_HT_MCS14 (pAd->chipCap.PAModeHT[14])
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#define RF_PA_MODE_HT_MCS15 (pAd->chipCap.PAModeHT[15])
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enum TEMPERATURE_MODE {
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TEMPERATURE_MODE_NORMAL,
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TEMPERATURE_MODE_LOW,
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TEMPERATURE_MODE_HIGH,
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};
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#ifdef RTMP_INTERNAL_TX_ALC
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#define DEFAULT_BO 4
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#define LIN2DB_ERROR_CODE (-10000)
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VOID MT7601_TssiDcGainCalibration(struct _RTMP_ADAPTER *pAd);
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typedef struct _MT7601_TX_ALC_DATA {
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INT32 PowerDiffPre;
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INT32 MT7601_TSSI_T0_Delta_Offset;
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INT16 TSSI_DBOFFSET_HVGA;
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INT16 TSSI0_DB;
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UCHAR TssiSlope;
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CHAR TssiDC0;
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CHAR TssiDC0_HVGA;
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UINT32 InitTxAlcCfg1;
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BOOLEAN TSSI_USE_HVGA;
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BOOLEAN TssiTriggered;
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CHAR MT7601_TSSI_OFFSET[3];
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} MT7601_TX_ALC_DATA, *PMT7601_TX_ALC_DATA;
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#endif /* RTMP_INTERNAL_TX_ALC */
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/*
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rsv: Reserved
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tcp: packet type, tcp : 1, udp:0
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tups: TCP/UDP header start offset (in unit of DWORD)
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ips: IP start offset (in unit of byte), base address of ips is the beginning of TXWI
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mss: Max Segment size (in unit of byte)
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*/
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#ifdef RT_BIG_ENDIAN
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typedef struct _TSO_INFO_{
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UINT32 mss:16;
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UINT32 ips:8;
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UINT32 tups:6;
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UINT32 tcp:1;
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UINT32 rsv:1;
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}TSO_INFO;
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#else
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typedef struct _TSO_INFO_{
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UINT32 rsv:1;
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UINT32 tcp:1;
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UINT32 tups:6;
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UINT32 ips:8;
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UINT32 mss:16;
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}TSO_INFO;
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#endif /* RT_BIG_ENDIAN */
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/*
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* Frequency plan item for MT7601
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* K_R17[7:0]: sdm_k[7:0]
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* K_R18[7:0]: sdm_k[15:8]
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* K_R19[1:0]: sdm_k[17:16]
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* K_R19[3]: sdm_clk_sel
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* R_R20[7:0]: sdm_n[7:0]
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*/
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typedef struct _MT7601_FREQ_ITEM {
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UINT8 Channel;
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UINT8 K_R17;
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UINT8 K_R18;
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UINT8 K_R19;
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UINT8 N_R20;
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} MT7601_FREQ_ITEM;
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#define RF_G_BAND 0x01
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#define RF_A_BAND 0x02
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#define RF_A_BAND_LB 0x04
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#define RF_A_BAND_MB 0x08
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#define RF_A_BAND_HB 0x10
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typedef struct _RT6590_RF_SWITCH_ITEM {
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UCHAR Bank;
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UCHAR Register;
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UCHAR Band; /* G_Band, A_Band_LB, A_Band_MB, A_Band_HB */
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UCHAR BW;
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UCHAR Value;
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} RT6590_RF_SWITCH_ITEM, *PRT6590_RF_SWITCH_ITEM;
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VOID MT7601_Init(struct _RTMP_ADAPTER *pAd);
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VOID MT7601_RXDC_CAL(struct _RTMP_ADAPTER *pAd);
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INT MT7601_ReadChannelPwr(struct _RTMP_ADAPTER *pAd);
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VOID MT7601_ReadTxPwrPerRate(struct _RTMP_ADAPTER *pAd);
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VOID MT7601_INIT_CAL(struct _RTMP_ADAPTER *pAd);
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NTSTATUS MT7601DisableTxRx(struct _RTMP_ADAPTER *pAd, UCHAR Level);
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VOID dump_bw_info(struct _RTMP_ADAPTER *pAd);
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VOID MT7601AsicTemperatureCompensation(IN struct _RTMP_ADAPTER *pAd, IN BOOLEAN bPowerOn);
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#ifdef RTMP_INTERNAL_TX_ALC
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INT16 lin2dBd(UINT16 linearValue);
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VOID MT7601_EnableTSSI(struct _RTMP_ADAPTER *pAd);
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#endif /* RTMP_INTERNAL_TX_ALC */
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#if defined(RTMP_INTERNAL_TX_ALC) || defined(SINGLE_SKU_V2)
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VOID MT7601_InitPAModeTable(struct _RTMP_ADAPTER *pAd);
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#endif /* defined(RTMP_INTERNAL_TX_ALC) || defined(SINGLE_SKU_V2) */
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#ifdef MICROWAVE_OVEN_SUPPORT
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VOID MT7601_AsicMitigateMicrowave(
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IN struct _RTMP_ADAPTER *pAd);
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VOID MT7601_AsicMeasureFalseCCA(
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IN struct _RTMP_ADAPTER *pAd);
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#endif /* MICROWAVE_OVEN_SUPPORT */
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INT MT7601_Read_Temperature(
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struct _RTMP_ADAPTER *pAd,
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OUT CHAR* Temperature);
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INT MT7601_Bootup_Read_Temperature(
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struct _RTMP_ADAPTER *pAd,
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OUT CHAR* Temperature);
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VOID MT7601SetRxAnt(
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struct _RTMP_ADAPTER *pAd,
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IN UCHAR Ant);
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#endif /* __MT7601_H__ */
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