399 lines
13 KiB
C++
399 lines
13 KiB
C++
// I2Cdev library collection - L3GD20H I2C device class header file
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// Based on STMicroelectronics L3GD20H datasheet rev. 2, 3/2013
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// 3/05/2015 by Nate Costello <natecostello at gmail dot com>
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// Updates should (hopefully) always be available at https://github.com/jrowberg/i2cdevlib
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//
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// Changelog:
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// 2015-03-05 - initial release
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/* ============================================
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I2Cdev device library code is placed under the MIT license
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Copyright (c) 2011 Jonathan Arnett, Jeff Rowberg
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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===============================================
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*/
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#ifndef _L3GD20H_H_
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#define _L3GD20H_H_
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#include "I2Cdev.h"
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#define L3GD20H_ADDRESS 0x6B // I think this is correct. See SAD in doc.
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#define L3GD20H_DEFAULT_ADDRESS 0x6B // I think this is correct. See SAD in doc.
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#define L3GD20H_RA_WHO_AM_I 0x0F
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#define L3GD20H_RA_CTRL1 0x20
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#define L3GD20H_RA_CTRL2 0x21
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#define L3GD20H_RA_CTRL3 0x22
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#define L3GD20H_RA_CTRL4 0x23
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#define L3GD20H_RA_CTRL5 0x24
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#define L3GD20H_RA_REFERENCE 0x25
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#define L3GD20H_RA_OUT_TEMP 0x26
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#define L3GD20H_RA_STATUS 0x27
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#define L3GD20H_RA_OUT_X_L 0x28
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#define L3GD20H_RA_OUT_X_H 0x29
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#define L3GD20H_RA_OUT_Y_L 0x2A
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#define L3GD20H_RA_OUT_Y_H 0x2B
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#define L3GD20H_RA_OUT_Z_L 0x2C
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#define L3GD20H_RA_OUT_Z_H 0x2D
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#define L3GD20H_RA_FIFO_CTRL 0x2E
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#define L3GD20H_RA_FIFO_SRC 0x2F
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#define L3GD20H_RA_IG_CFG 0x30
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#define L3GD20H_RA_IG_SRC 0x31
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#define L3GD20H_RA_IG_THS_XH 0x32
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#define L3GD20H_RA_IG_THS_XL 0X33
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#define L3GD20H_RA_IG_THS_YH 0X34
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#define L3GD20H_RA_IG_THS_YL 0x35
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#define L3GD20H_RA_IG_THS_ZH 0X36
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#define L3GD20H_RA_IG_THS_ZL 0x37
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#define L3GD20H_RA_IG_DURATION 0X38
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#define L3GD20H_RA_LOW_ODR 0x39
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#define L3GD20H_ODR_BIT 7
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#define L3GD20H_ODR_LENGTH 2
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#define L3GD20H_BW_BIT 5
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#define L3GD20H_BW_LENGTH 2
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#define L3GD20H_PD_BIT 3
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#define L3GD20H_ZEN_BIT 2
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#define L3GD20H_YEN_BIT 1
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#define L3GD20H_XEN_BIT 0
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#define L3GD20H_RATE_100_12 0b00 //selection of high vs low rate is via Low_ODR
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#define L3GD20H_RATE_200_25 0b01 //selection of high vs low rate is via Low_ODR
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#define L3GD20H_RATE_400_50 0b10 //selection of high vs low rate is via Low_ODR
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#define L3GD20H_RATE_800_50 0b11 //selection of high vs low rate is via Low_ODR
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#define L3GD20H_BW_LOW 0b00
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#define L3GD20H_BW_MED_LOW 0b01
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#define L3GD20H_BW_MED_HIGH 0b10
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#define L3GD20H_BW_HIGH 0b11
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#define L3GD20H_HPM_BIT 5
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#define L3GD20H_HPM_LENGTH 2
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#define L3GD20H_HPCF_BIT 3
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#define L3GD20H_HPCF_LENGTH 4
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#define L3GD20H_HPM_HRF 0b00 //this resets on reading REFERENCE
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#define L3GD20H_HPM_REFERENCE 0b01
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#define L3GD20H_HPM_NORMAL 0b10
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#define L3GD20H_HPM_AUTORESET 0b11
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#define L3GD20H_HPCF1 0b0000
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#define L3GD20H_HPCF2 0b0001
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#define L3GD20H_HPCF3 0b0010
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#define L3GD20H_HPCF4 0b0011
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#define L3GD20H_HPCF5 0b0100
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#define L3GD20H_HPCF6 0b0101
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#define L3GD20H_HPCF7 0b0110
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#define L3GD20H_HPCF8 0b0111
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#define L3GD20H_HPCF9 0b1000
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#define L3GD20H_HPCF10 0b1001
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#define L3GD20H_INT1_IG_BIT 7
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#define L3GD20H_INT1_BOOT_BIT 6
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#define L3GD20H_H_LACTIVE_BIT 5
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#define L3GD20H_PP_OD_BIT 4
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#define L3GD20H_INT2_DRDY_BIT 3
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#define L3GD20H_INT2_FTH_BIT 2
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#define L3GD20H_INT2_ORUN_BIT 1
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#define L3GD20H_INT2_EMPTY_BIT 0
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#define L3GD20H_PUSH_PULL 0
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#define L3GD20H_OPEN_DRAIN 1
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#define L3GD20H_BDU_BIT 7
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#define L3GD20H_BLE_BIT 6
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#define L3GD20H_FS_BIT 5
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#define L3GD20H_FS_LENGTH 2
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#define L3GD20H_IMPEN_BIT 3 //new for this IC: Level sensitive latched enalble
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#define L3GD20H_ST_BIT 2
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#define L3GD20H_ST_LENGTH 2
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#define L3GD20H_SIM_BIT 0
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#define L3GD20H_BIG_ENDIAN 1
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#define L3GD20H_LITTLE_ENDIAN 0
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#define L3GD20H_FS_250 0b00
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#define L3GD20H_FS_500 0b01
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#define L3GD20H_FS_2000 0b10
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#define L3GD20H_SELF_TEST_NORMAL 0b00
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#define L3GD20H_SELF_TEST_0 0b01
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#define L3GD20H_SELF_TEST_1 0b11
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#define L3GD20H_SPI_4_WIRE 0
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#define L3GD20H_SPI_3_WIRE 1
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#define L3GD20H_BOOT_BIT 7
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#define L3GD20H_FIFO_EN_BIT 6
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#define L3GD20H_STOPONFTH_BIT 5
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#define L3GD20H_HPEN_BIT 4
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#define L3GD20H_IG_SEL_BIT 3
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#define L3GD20H_IG_SEL_LENGTH 2
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#define L3GD20H_OUT_SEL_BIT 1
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#define L3GD20H_OUT_SEL_LENGTH 2
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#define L3GD20H_NON_HIGH_PASS 0b00
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#define L3GD20H_HIGH_PASS 0b01
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#define L3GD20H_LOW_PASS 0b10 //depends on HPEN
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#define L3GD20H_LOW_HIGH_PASS 0b11 //depends on HPEN
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#define L3GD20H_ZYXOR_BIT 7
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#define L3GD20H_ZOR_BIT 6
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#define L3GD20H_YOR_BIT 5
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#define L3GD20H_XOR_BIT 4
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#define L3GD20H_ZYXDA_BIT 3
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#define L3GD20H_ZDA_BIT 2
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#define L3GD20H_YDA_BIT 1
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#define L3GD20H_XDA_BIT 0
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#define L3GD20H_FIFO_MODE_BIT 7
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#define L3GD20H_FIFO_MODE_LENGTH 3
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#define L3GD20H_FIFO_TH_BIT 4
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#define L3GD20H_FIFO_TH_LENGTH 5
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#define L3GD20H_FM_BYPASS 0b000
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#define L3GD20H_FM_FIFO 0b001
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#define L3GD20H_FM_STREAM 0b010
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#define L3GD20H_FM_STREAM_FIFO 0b011
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#define L3GD20H_FM_BYPASS_STREAM 0b100
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#define L3GD20H_FM_DYNAMIC_STREAM 0b110
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#define L3GD20H_FM_BYPASS_FIFO 0b111
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#define L3GD20H_FIFO_TH_STATUS_BIT 7
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#define L3GD20H_OVRN_BIT 6
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#define L3GD20H_EMPTY_BIT 5
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#define L3GD20H_FIFO_FSS_BIT 4
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#define L3GD20H_FIFO_FSS_LENGTH 5
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#define L3GD20H_AND_OR_BIT 7
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#define L3GD20H_LIR_BIT 6
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#define L3GD20H_ZHIE_BIT 5
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#define L3GD20H_ZLIE_BIT 4
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#define L3GD20H_YHIE_BIT 3
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#define L3GD20H_YLIE_BIT 2
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#define L3GD20H_XHIE_BIT 1
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#define L3GD20H_XLIE_BIT 0
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#define L3GD20H_AND_OR_OR 0
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#define L3GD20H_AND_OR_AND 1
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#define L3GD20H_IA_BIT 6
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#define L3GD20H_ZH_BIT 5
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#define L3GD20H_ZL_BIT 4
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#define L3GD20H_YH_BIT 3
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#define L3GD20H_YL_BIT 2
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#define L3GD20H_XH_BIT 1
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#define L3GD20H_XL_BIT 0
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#define L3GD20H_DCRM_BIT 7
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#define L3GD20H_DCRM_RESET 0
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#define L3GD20H_DCRM_DEC 1
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#define L3GD20H_WAIT_BIT 7
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#define L3GD20H_DUR_BIT 6
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#define L3GD20H_DUR_LENGTH 7
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#define L3GD20H_LOW_ODR_BIT 0
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#define L3GD20H_SW_RESET_BIT 2
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#define L3GD20H_I2C_DIS_BIT 3
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#define L3GD20H_DRDY_HL_BIT 5
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class L3GD20H {
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public:
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L3GD20H();
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L3GD20H(uint8_t address);
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void initialize();
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bool testConnection();
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// WHO_AM_I register, read-only
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uint8_t getDeviceID();
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// CTRL1 register, r/w
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void setOutputDataRate(uint16_t rate);
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uint16_t getOutputDataRate();
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void setBandwidthCutOffMode(uint8_t mode);
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uint8_t getBandwidthCutOffMode();
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// float getBandwidthCutOff();
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void setPowerOn(bool on);
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bool getPowerOn();
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void setZEnabled(bool enabled);
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bool getZEnabled();
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void setYEnabled(bool enabled);
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bool getYEnabled();
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void setXEnabled(bool enabled);
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bool getXEnabled();
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// CTRL2 register, r/w
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void setHighPassMode(uint8_t mode);
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uint8_t getHighPassMode();
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void setHighPassFilterCutOffFrequencyLevel(uint8_t level);
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uint8_t getHighPassFilterCutOffFrequencyLevel();
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// CTRL3 register, r/w
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void setINT1InterruptEnabled(bool enabled);
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bool getINT1InterruptEnabled();
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void setINT1BootStatusEnabled(bool enabled);
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bool getINT1BootStatusEnabled();
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void interruptActiveINT1Config();
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void setOutputMode(bool mode);
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bool getOutputMode();
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void setINT2DataReadyEnabled(bool enabled);
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bool getINT2DataReadyEnabled();
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void setINT2FIFOWatermarkInterruptEnabled(bool enabled);
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bool getINT2FIFOWatermarkInterruptEnabled();
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void setINT2FIFOOverrunInterruptEnabled(bool enabled);
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bool getINT2FIFOOverrunInterruptEnabled();
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void setINT2FIFOEmptyInterruptEnabled(bool enabled);
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bool getINT2FIFOEmptyInterruptEnabled();
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// CTRL4 register, r/w
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void setBlockDataUpdateEnabled(bool enabled);
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bool getBlockDataUpdateEnabled();
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void setEndianMode(bool endianness);
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bool getEndianMode();
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void setFullScale(uint16_t scale);
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uint16_t getFullScale();
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void setSelfTestMode(uint8_t mode);
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uint8_t getSelfTestMode();
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void setSPIMode(bool mode);
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bool getSPIMode();
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// CTRL5 register, r/w
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void rebootMemoryContent();
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void setFIFOEnabled(bool enabled);
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bool getFIFOEnabled();
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void setStopOnFIFOThresholdEnabled(bool enabled);
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bool getStopOnFIFOThresholdEnabled();
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void setHighPassFilterEnabled(bool enabled);
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bool getHighPassFilterEnabled();
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void setDataFilter(uint8_t filter);
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uint8_t getDataFilter();
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// REFERENCE/DATACAPTURE register, r/w
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void setHighPassFilterReference(uint8_t reference);
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uint8_t getHighPassFilterReference();
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// OUT_TEMP register, read-only
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uint8_t getTemperature();
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// STATUS register, read-only
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bool getXYZOverrun();
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bool getZOverrun();
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bool getYOverrun();
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bool getXOverrun();
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bool getXYZDataAvailable();
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bool getZDataAvailable();
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bool getYDataAvailable();
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bool getXDataAvailable();
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// OUT_* registers, read-only
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void getAngularVelocity(int16_t* x, int16_t* y, int16_t* z);
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int16_t getAngularVelocityX();
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int16_t getAngularVelocityY();
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int16_t getAngularVelocityZ();
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// FIFO_CTRL register, r/w
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void setFIFOMode(uint8_t mode);
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uint8_t getFIFOMode();
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void setFIFOThreshold(uint8_t wtm);
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uint8_t getFIFOThreshold();
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// FIFO_SRC register, read-only
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bool getFIFOAtWatermark();
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bool getFIFOOverrun();
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bool getFIFOEmpty();
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uint8_t getFIFOStoredDataLevel();
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// IG_CFG register, r/w
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void setInterruptCombination(bool combination);
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bool getInterruptCombination();
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void setInterruptRequestLatched(bool latched);
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bool getInterruptRequestLatched();
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void setZHighInterruptEnabled(bool enabled);
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bool getZHighInterruptEnabled();
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void setYHighInterruptEnabled(bool enabled);
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bool getYHighInterruptEnabled();
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void setXHighInterruptEnabled(bool enabled);
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bool getXHighInterruptEnabled();
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void setZLowInterruptEnabled(bool enabled);
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bool getZLowInterruptEnabled();
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void setYLowInterruptEnabled(bool enabled);
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bool getYLowInterruptEnabled();
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void setXLowInterruptEnabled(bool enabled);
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bool getXLowInterruptEnabled();
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// IG_SRC register, read-only
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bool getInterruptActive();
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bool getZHigh();
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bool getZLow();
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bool getYHigh();
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bool getYLow();
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bool getXHigh();
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bool getXLow();
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// IG_THS_* registers, r/w
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void setDecrementMode(bool mode);
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bool getDecrementMode();
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void setXHighThreshold(uint8_t threshold);
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uint8_t getXHighThreshold();
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void setXLowThreshold(uint8_t threshold);
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uint8_t getXLowThreshold();
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void setYHighThreshold(uint8_t threshold);
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uint8_t getYHighThreshold();
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void setYLowThreshold(uint8_t threshold);
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uint8_t getYLowThreshold();
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void setZHighThreshold(uint8_t threshold);
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uint8_t getZHighThreshold();
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void setZLowThreshold(uint8_t threshold);
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uint8_t getZLowThreshold();
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// IG_DURATION register, r/w
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void setDuration(uint8_t duration);
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uint8_t getDuration();
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void setWaitEnabled(bool enabled);
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bool getWaitEnabled();
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// LOW_ODR register, r/w
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void setINT2DataReadyActiveLowEnabled(bool enabled);
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bool getINT2DataReadyActiveLowEnabled();
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void setSPIOnlyEnabled(bool enabled);
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bool getSPIOnlyEnabled();
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void setSoftwareReset(bool reset);
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void setLowODREnabled(bool enabled);
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bool getLowODREnabled();
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private:
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uint8_t devAddr;
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uint8_t buffer[6];
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bool endianMode;
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};
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#endif /* _L3GD20H_H_ */
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